Input buffer with selectable threshold and hysteresis option
AssigneeAltera Corporation
InventorRafael C. Camarota
Life of this patent
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Abstract
An input buffer is configurable for use as a standard buffer with a single switching threshold, selectable to be one of at least two different switching thresholds, or used as a Schmitt trigger circuit with hysteresis, which uses at least two switching thresholds from among the at least two different switching thresholds. The integrated circuit may be a programmable logic device (PLD) or field programmable gate array (FPGA), but in other embodiments, the integrated circuit may be other types of devices such a microprocessors, ASICs, or memories.
Claims20
A programmable logic integrated circuit comprising:
- a plurality of programmable interconnect lines;
- a plurality of logic array blocks, programmably coupled to the programmable interconnect lines;
- and
- a plurality of input blocks, programmably coupled to the plurality of logic array blocks, wherein signals output from the input blocks are programmably coupled using the programmable interconnect lines to input to the plurality of logic array blocks, an input block comprising:
- a first buffer configured to receive an input signal and to provide a first output signal having a first polarity when the input signal is below a first switching threshold level, and provide a second polarity when the input signal is above the first switching threshold level;
- a second buffer configured to receive the input signal and to provide a second output signal at third polarity when the input signal is below a second switching threshold level, and provide the output signal at a fourth polarity when the input signal is above the second switching threshold level, wherein the second switching threshold level is different from the first switching threshold level;
- a first multiplexer having inputs coupled to the first and second buffers;
- and
- a third buffer coupled to an output of the multiplexer, wherein an output of the third buffer is programmably coupled to a control input of the first multiplexer, wherein the third buffer is programmably coupled to an output of the first buffer or an output of the second buffer though the first multiplexer.
A method of operating an integrated circuit comprising:
- providing an input buffer capable of operating as a standard buffer having one of at least two different switching thresholds in a first mode or a Schmitt trigger in a second mode;
- configuring a mode bit to control whether the input buffer operates in the first mode or the second mode;
- and
- when in the second mode, feeding back an output from a buffer to a control input of a multiplexer circuit.
A integrated circuit comprising:
- a first inverter buffer having a first switching threshold level;
- a second inverter buffer having a second switching threshold level, different from the first switching threshold level;
- a first multiplexer having inputs coupled to the first and second inverter buffers;
- a third inverter buffer coupled to an output of the multiplexer;
- a second multiplexer comprising an output coupled to a control input of the first multiplexer, and inputs coupled to a first memory bit and an output of the third inverter buffer;
- and
- a second memory bit coupled to a control input of the second multiplexer.
Dependencies are inferred from the claim text.