Redundant single event upset supression system
AssigneeUniversities Research Association, Inc.
InventorJames R. Hoff
Life of this patent
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Abstract
CMOS transistors are configured to operate as either a redundant, SEU-tolerant, positive-logic, cross-coupled Nor Gate SR-flip flop or a redundant, SEU-tolerant, negative-logic, cross-coupled Nand Gate SR-flip flop. The register can operate as a memory, and further as a memory that can overcome the effects of radiation. As an SR-flip flop, the invention can be altered into any known type of latch or flip-flop by the application of external logic, thereby extending radiation tolerance to devices previously incapable of radiation tolerance. Numerous registers can be logically connected and replicated thereby being electronically configured to operate as a redundant circuit.
Claims10
A system comprising:
- transistors adapted to operate as an SR flip-flop wherein each one of the transistors has an insulated gate and wherein the SR flip-flop is a SEUSSNor comprising:
- a power node and four p type transistors named P2, P4, P6, and P8 wherein the sources of P2, P4, P6, and P8 are connected to the power node;
- a ground node and eight n type transistors named N1, N2, N3, N4, N5, N6, N7, and N8 wherein the sources of N1, N2, N3, N4, N5, N6, N7, and N8 are connected to the ground node;
- a p type transistor called P1 wherein the source of P1 is connected to the drain of P2;
- a p type transistor called P3 wherein the source of P3 is connected to the drain of P4;
- a p type transistor called P5 wherein the source of P5 is connected to the drain of P6;
- a p type transistor called P7 wherein the source of P7 is connected to the drain of P8;
- an S input connected to the gate of P1, the gate of N1, the gate of N5 and the gate of P5;
- an R input connected to the gate of P3, the gate of N3, the gate of N7 and the gate of P7;
- a Q2 node connected to the gate of P2, the gate of N6, the drain of N7, the drain of P7, and the drain of N8;
- a Qbar node connected to the gate of P4, the gate of N8, the drain of N1, the drain of P1, and the drain of N2;
- a Q node connected to the gate of P6, the gate of N2, the drain of N3, the drain of P3, and the drain of N4;
- and
- a Qbar2 node connected to the gate of P8, the gate of N4, the drain of N5, the drain of P5, and the drain of N6.
A system comprising:
- transistors adapted to operate as an SR flip-flop wherein each one of the transistors comprises has an insulated gate and wherein the SR flip-flop is a SEUSSNand comprising:
- a power node and eight p type transistors named P1, P2, P3, P4, P5, P6, P7, and P8 wherein the sources of P1, P2, P3, P4, P5, P6, P7, and P8 are connected to the power node;
- a ground node and four n type transistors named N2, N4, N6, and N8 wherein the sources of N2, N4, N6, and N8 are connected to the ground node;
- an n type transistor called N1 wherein the source of N1 is connected to the drain of N2;
- an n type transistor called N3 wherein the source of N3 is connected to the drain of N4;
- an n type transistor called N5 wherein the source of N5 is connected to the drain of N6;
- an n type transistor called N7 wherein the source of N7 is connected to the drain of N8;
- an S input connected to the gate of P1, the gate of N1, the gate of N5 and the gate of P5;
- an R input connected to the gate of P3, the gate of N3, the gate of N7 and the gate of P7;
- a Qbar2 node connected to the gate of P2, the gate of N6, the drain of P7, the drain of N7, and the drain of P8;
- a Q node connected to the gate of P4, the gate of N8, the drain of N1, the drain of P1, and the drain of P2;
- a Qbar node connected to the gate of P6, the gate of N2, the drain of N3, the drain of P3, and the drain of P4;
- and
- a Q2 output node connected to the gate of P8, the gate of N4, the drain of N5, the drain of P5, and the drain of P6.
Dependencies are inferred from the claim text.