US 7,023,195 B2 · Module, system and method for testing a phase locked loop

Abstract

A digital test module (5) is provided for testing a phase locked loop circuit. The module (5) includes phase detection circuitry (10) for performing phase measurements of the phase locked loop circuit and analog test circuitry (20) for testing at least one analog element of the phase locked loop circuit. Frequency measurement circuitry (30) is provided for performing frequency measurements of the phase locked loop circuit, as is circuitry (40) for performing calibration and jitter measurements. In this way cycle-to-cycle and phase jitter measurements may be made. A calibration mechanism is provided allowing a process evaluation to be made and which allows the jitter data to be provided in a few seconds. The fully digital design facilitates easy manufacture and ready retargeting of the module to diverse applications and processes.

Claims8

Dependent claims

A digital test module for testing

a phase locked loop circuit, the module comprising:
phase detection means for performing phase measurements of the phase locked loop circuit;
analogue test means for testing at least one analogue element of the phase locked loop circuit,
wherein the analogue test means comprises:
a test controller arranged to perform testing of the at least one analogue element;
a first digital-to-analogue converter coupled to the test controller and arranged for providing a first analogue output;
and
a second digital-to-analogue convener coupled to the test controller and arranged for providing a second analogue output, wherein the first and second analogue outputs are used in combination to test the at least one analogue element;
frequency measurement means for performing frequency measurements of the phase locked loop circuit;
and
means for performing calibration and jitter measurements.

8 more elements

Dependencies are inferred from the claim text.

Module, system and method for testing a phase locked loop

Life of this patent

Module, system and method for testing a phase locked loop

Life of this patent

Abstract

Claims8