Multi-chip package having spacer that is inserted between chips and manufacturing method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsKyu Jin Lee, Hyung Jik Byun
Life of this patent
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Abstract
A multi-chip package includes a substrate with a chip mounting area and a first chip positioned in the mounting area. A spacer is attached to the active surface of the first chip and has a thickness to allow space for wire-bonding the first chip's active surface to the substrate. A second chip is attached to the spacer over the first chip. Conductive metal wires electrically connect the first and second chips to the substrate. A package body is formed by encapsulating the first and second chips and the conductive metal wires. Ends of the spacer extend to the edge the package body. External connection terminals are attached to the bottom surface of the substrate and a method for the manufacturing thereof.
Claims12
A multi-chip comprising:
- a substrate having a top surface and a bottom surface;
- a first chip attached to the top surface of the substrate, wherein the first chip comprises an active surface;
- a spacer mounted on the active surface of the first chip;
- a second chip comprising an active surface and a back surface, wherein the back surface of the second chip is mounted on the spacer;
- and
- a package body formed by encapsulating the first chip and the second chip,
- wherein side surface of the ends of the spacer are exposed to outside of the package body.
Dependencies are inferred from the claim text.