US 7,023,091 B2Granted

Semiconductor integrated circuit device

AssigneeRenesas Technology Corp.

InventorsTakako Funakoshi, Eiichi Murakami, Kazumasa Yanagisawa, Kan Takeuchi, Hideo Aoki, Hizuru Yamaguchi, Takayuki Oshima, Kazuyuki Tsunokuni

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Abstract

In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Claims11

Dependent claims

A semiconductor integrated circuit device comprising:

a first buried wiring formed in the interior of a first wiring groove formed in a first insulating film, wherein the first buried wiring includes first and second ends in a width direction;
a second insulating film formed in a layer overlying the first insulating film;
a third insulating film formed in a layer overlying the second insulating film;
a second buried wiring formed in the interior of a second wiring groove formed in the third insulating film;
and
a first plug formed in the interior of a first hole formed in the second insulating film to connect the first buried wiring and the second buried wiring electrically with each other,
wherein a first position at which the first plug and the first buried wiring are connected with each other is positioned so that the first position is not over the center of the first buried wiring in the width direction of the first buried wiring, and is closer to one of the first and second ends than to the other of the first and second ends of the first buried wiring when viewed in a plane view, and wherein the first position is positioned at a center portion in the width direction of the second buried wiring in a plane view.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/465,541Filed 20 Jun 2003
Priority: JP 2002-18197421 Jun 2002
Published: US 2004/0065961 A18 Apr 2004
Granted: 4 Apr 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10W 20/425
Characterised by their conductive parts: barrier, adhesion or liner layers
H10D 84/0186
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their interconnections or electrodes, e.g. source or drain electrodes
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10W 20/42
Characterised by their conductive parts: vias, e.g. via plugs