US 7,023,082 B2 · Semiconductor package and manufacturing method thereof

Abstract

A semiconductor package mainly comprises a substrate unit and a chip. The chip is electrically connected to the substrate unit. The substrate unit includes an upper surface, a lower surface and a side surface. A plurality of circuit traces are formed on the upper surface and a plurality of contacts are formed on the side surface, wherein the contacts are electrically connected to the circuit traces. Besides, a plurality of solder balls are formed on the contacts in order to transmit the signals from chip to outside through the substrate unit, the contacts and the solder balls. Furthermore, a semiconductor package module will be formed by electrically connecting the semiconductor packages with each other through solder balls and a module substrate, and mounting the semiconductor packages with each other through an adhesive layer. In addition, a method for manufacturing the semiconductor package is disclosed.

Claims10

Dependent claims

A semiconductor package, comprising:

a substrate unit having an upper surface, a lower surface, a side surface connecting the upper surface and the lower surface, a plurality of circuit traces formed on the upper surface, a plurality of recesses formed on the side surface and electrically connecting to the circuit traces, and a metal layer formed on each of the recesses;
and
a chip having an active surface and a back surface, wherein a plurality of bonding pads are formed on the active surface, a plurality of bumps formed on the bonding pads and the active surface of the chip faces to the upper surface of the substrate and is electrically connected to the substrate via the bumps.

A semiconductor package module, comprising:

a first substrate unit having a first upper surface, a first lower surface, a first side surface connecting the first upper surface and the first lower surface, a plurality of first circuit traces formed on the first upper surface, and a plurality of first contacts formed on the first side surface and electrically connecting to the first circuit traces;
a first chip having a first active surface and a first back surface, and disposed on the first upper surface of the first substrate unit and electrically connected to the first substrate unit;
a second substrate unit having a second upper surface, a second lower surface, a second side surface connecting the second upper surface and the second lower surface, a plurality of second circuit traces formed on the second upper surface, and a plurality of second contacts formed on the second side surface and electrically connecting to the second circuit traces;
a second chip having a second active surface and a second back surface, and disposed on the second upper surface of the second substrate unit and electrically connected to the second substrate unit;
a plurality of first electrically conductive devices formed on the first contacts;
and
a plurality of second electrically conductive devices formed on the second contacts.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor package and manufacturing method thereof

Life of this patent

Semiconductor package and manufacturing method thereof

Life of this patent

Abstract

Claims10