US 7,023,071 B2 · Semiconductor integrated circuit device and process for manufacturing the same · patentgrep

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Abstract

A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Claims30

Dependent claims

A semiconductor integrated circuit device comprising:

a plurality of memory cells arranged in a first direction and in a second direction crossing said first direction,
each of said plurality of memory cells including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET, a second p-channel MISFET, a first conductive film and a second conductive film,
said first n-channel MISFET and said second n-channel MISFET each having a gate electrode formed on a semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate,
said first p-channel MISFET and said second p-channel MISFET each having a gate electrode formed on said semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate,
said first n-channel MISFET and said second n-channel MISFET spaced from said first p-channel MISFET and said second p-channel MISFET in said first direction,
said first conductive film and said second conductive film located on said semiconductor substrate and comprised of a different conductive layer from the gate electrodes of the MISFETS, with an insulating film interposed therebetween,
said first conductive film being electrically connected to said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET,
said second conductive film being electrically connected to said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET;
and
a capacitor electrode, of capacitor elements, extending over adjacent memory cells arranged in said first direction such that said capacitor electrode extends over the first conductive films and the second conductive films in said adjacent memory cells arranged in said first direction,
said capacitor elements comprising said capacitor electrode and said first conductive films of said memory cells, and
said capacitor elements also comprising said capacitor electrode and said second conductive films of said memory cells.

9 more elements

A semiconductor integrated circuit device comprising:

a plurality of memory cells arranged in a first direction and in a second direction crossing said first direction,
each of said plurality of memory cells including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET, a second p-channel MISFET, a first conductive film and a second conductive film,
said first n-channel MISFET and said second n-channel MISFET each having a gate electrode formed on a semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate,
said first p-channel MISFET and said second p-channel MISFET each having a gate electrode formed on said semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate,
said first conductive film and said second conductive film located on said semiconductor substrate and comprised of a different conductive layer from the gate electrodes of the MISFETs, with an insulating film interposed therebetween,
said first conductive film being electrically connected to said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET,
said second conductive film being electrically connected to said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET;
and
a capacitor electrode, of capacitor elements, extending over adjacent memory cells arranged in said first direction and adjacent memory cells arranged in said second direction such that said capacitor electrode extends over the first conductive films and the second conductive films in said adjacent memory cells arranged in said first direction and said adjacent memory cells arranged in said second direction,
said capacitor elements comprising said capacitor electrode and said first conductive films of said memory cells,
said capacitor elements also comprising said capacitor electrode and said second conductive films of said memory cells.

8 more elements

A semiconductor integrated circuit device comprising:

memory cells arranged in a first direction and in a second direction crossing said first direction,
each of said memory cells including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET, a second p-channel MISFET, a first conductive film and a second conductive film,
said first n-channel MISFET and said second n-channel MISFET each having a gate electrode formed on a semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate,
said first p-channel MISFET and said second p-channel MISFET each having a gate electrode formed on said semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate,
said first conductive film and said second conductive film located on said semiconductor substrate and comprised of a different conductive layer from the gate electrodes of the MISFETs, with an insulating film Interposed therebetween,
said first conductive film being electrically connected to said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET,
said second conductive film being electrically connected to said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET;
and
a capacitor electrode, of capacitor elements, extending over adjacent memory cells arranged in a first direction such that said capacitor electrode covers substantially all the first conductive films and the second conductive films in said adjacent memory cells arranged in said first direction,
said capacitor elements comprising said capacitor electrode and said first conductive films of said memory cells, and
said capacitor elements also comprising said capacitor electrode and said second conductive films of said memory cells.

8 more elements

A semiconductor integrated circuit device comprising:

memory cells arranged in a first direction and in a second direction crossing said first direction,
each of said memory cells including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET, a second p-channel MISFET, a first conductive film and a second conductive film,
said first n-channel MISFET and said second n-channel MISFET each having a gate electrode located on a semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate,
said first n-channel MISFET and said second n-channel MISFET arranged to be spaced from said first p-channel MISFET and said second p-channel MISFET in said first direction,
said first p-channel MISFET and said second p-channel MISFET each having a gate electrode formed on said semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate;
a first insulating film formed on said gate electrodes of said first and second n-channel MISFETs and said first and second p-channel MISFETs,
said first conductive film located on said first insulating film and electrically connected to said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET,
said second conductive film located on said first insulating film and electrically connected to said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET;
and
a capacitor electrode, of capacitor elements, extending over adjacent memory cells arranged in said first direction such that said capacitor electrode is formed to cover the first conductive films and the second conductive films in said adjacent memory cells arranged in said first direction,
said capacitor elements comprising said capacitor electrode and said first conductive films of said memory cells, and
said capacitor elements also comprising said capacitor electrode and said second conductive films of said memory cells.

9 more elements

A semiconductor integrated circuit device comprising:

memory cells arranged in a first direction and in a second direction crossing said first direction,
each of said memory cells including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET, a second p-channel MISFET, a first conductive film and a second conductive film,
said first n-channel MISFET and said second n-channel MISFET each having a gate electrode on a semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate,
said first p-channel MISFET and said second p-channel MISFET each having a gate electrode on said semiconductor substrate, and a source region and a drain region in said semiconductor substrate,
said first n-channel MISFET and said second n-channel MISFET arranged to be spaced from said first p-channel MISFET and said second p-channel MISFET in said first direction,
said first conductive film and said second conductive film being on said semiconductor substrate and comprised of a different conductive layer from said gate electrodes of the MISFETs with an insulating film interposed therebetween,
said first conductive film being electrically connected to said drain region of said first n-channel MISFET said drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET,
said second conductive film being electrically connected to said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET;
and
a capacitor electrode, of capacitor elements, extending over adjacent memory cells arranged in said first direction such that said capacitor electrode extends over the first conductive films and the second conductive films in said adjacent memory cells arranged in said first direction and such that said capacitor electrode is formed over said drain regions of said first and second n-channel MISFETs and said first and second p-channel MISFET in said adjacent memory cells arranged in said first direction,
said capacitor elements comprising said capacitor electrode and the first conductive films of said memory cells,
said capacitor elements also comprising said capacitor electrode and the second conductive films of said memory cells.

9 more elements

A semiconductor integrated circuit device comprising:

memory cells arranged in a first direction and in a second direction crossing said first direction,
each of said memory cells including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET, a second p-channel MISFET, a first conductive film and a second conductive film,
said first n-channel MISFET and said second n-channel MISFET each having a gate electrode on a semiconductor substrate, and a source region and a drain region in said semiconductor substrate,
said first p-channel MISFET and said second p-channel MISFET each having a gate electrode formed on said semiconductor substrate, and a source region and a drain region in said semiconductor substrate,
said first n-channel MISFET and said second n-channel MISFET being spaced from said first p-channel MISFET and said second p-channel MISFET in said first direction,
said first conductive film and said second conductive film located on said semiconductor substrate and comprised of a different conductive layer from the gate electrodes of the MISFETs with an insulating film interposed therebetween,
said first conductive film being electrically connected to said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET,
said second conductive film being electrically connected to said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET;
and
a capacitor electrode, of capacitor elements, extending over adjacent memory cells arranged in said first direction such that said capacitor electrode extends over the first conductive films and the second conductive films in said adjacent memory cells arranged in said first direction and in said second direction and such that said capacitor electrode is formed over said drain regions of said first and second n-channel MISFETs and said first and second p-channel MISFETs in said adjacent memory cells arranged in said first direction and in said second direction,
said capacitor elements comprising said capacitor electrode and said first conductive films of said memory cells, and
said capacitor elements also comprising said capacitor electrode and said second conductive films of said memory cells.

9 more elements

A semiconductor integrated circuit device, comprising:

a plurality of memory cells arranged in a first direction and in a second direction crossing said first direction,
a memory cell, of said memory cells, including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET, a second p-channel MISFET, a first conductive film and a second conductive film,
each of the first and second n-channel MISFETs having a gate electrode formed on a semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate,
each of the first and second p-channel MISFETs having a gate electrode formed on said semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate,
said first and second n-channel MISFETs being arranged to be spaced from said first and said second p-channel MISFETs in said first direction,
said first conductive film and said second conductive film being located on said semiconductor substrate and comprised of a different conductive layer from the gate electrodes of said MISFETs with an insulating film interposed therebetween,
said first conductive film being electrically connected to said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET, and
said second conductive film being electrically connected to said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET;
and
a capacitor electrode of capacitor elements extending over adjacent memory cells, of said plurality of memory cells, that are arranged in said second direction, such that said capacitor electrode extends over said first conductive film and said second conductive film in said adjacent memory cells arranged in said second direction,
said capacitor elements comprising said capacitor electrode and said first conductive film of said memory cells, and
said capacitor elements also comprising said capacitor electrode and said second conductive film of said memory cells,
wherein said capacitor electrode covers substantially all of said first conductive film and said second conductive film in said adjacent memory cells arranged in said second direction.

10 more elements

A semiconductor integrated circuit device, comprising:

memory cells arranged in a first direction and in a second direction crossing said first direction,
a memory cell, of said memory cells, including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET, a second p-channel MISFET, a first conductive film and a second conductive film,
each of the first and second n-channel MISFETs having a gate electrode formed on a semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate,
each of the first and second n-channel MISFETs arranged to be spaced from said first and said second p-channel MISFETs in said first direction, and
each of the first and second p-channel MISFETs having a gate electrode formed on said semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate;
a first insulating film formed on said gate electrodes of said first and second n-channel MISFETS and said first and second p-channel MISFETs,
said first conductive film being located on said first insulating film and electrically connected to said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET, and
said second conductive film being located on said first insulating film and electrically connected to said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET;
and
a capacitor electrode of capacitor elements extending over adjacent memory cells, of said plurality of memory cells, that are arranged in said second direction, such that said capacitor electrode is over said first conductive film and said second conductive film in said adjacent memory cells arranged in said second direction,
said capacitor elements comprising said capacitor electrode and said first conductive film of said memory cells, and
said capacitor elements also comprising said capacitor electrode and said second conductive film of said memory cells,
wherein said capacitor electrode covers substantially all of the first and second conductive films in said adjacent memory cells arranged in said second direction.

10 more elements

A semiconductor integrated circuit device, comprising:

memory cells arranged in a first direction and in a second direction crossing said first direction,
a memory cell, of said memory cells, including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET, a second p-channel MISFET, a first conductive film and a second conductive film,
each of the first and second n-channel MISFETs having a gate electrode formed on a semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate,
each of the first and second p-channel MISFETs having a gate electrode formed on said semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate,
said first and second n-channel MISFETs being arranged to be spaced from said first and said second p-channel MISFETs in said first direction,
said first conductive film and said second conductive film being located on said semiconductor substrate and comprised of a different conductive layer from the gate electrodes of said MISFETs, with an insulating film interposed therebetween,
said first conductive film being electrically connected to said drain region of said first n-channel MISFET, said drain-region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET, and
said second conductive film being electrically connected to said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET;
and
a capacitor electrode of capacitor elements extending over adjacent memory cells, of said plurality of memory cells, that are arranged in said second direction, such that said capacitor electrode extends over said first conductive film and said second conductive film in said adjacent memory cells arranged in said second direction and such that said capacitor electrode is formed over said drain regions of said first and second n-channel MISFETs and said first and second p-channel MISFETs in said adjacent memory cells arranged in said second direction,
said capacitor elements comprising said capacitor electrode and said first conductive film of said memory cells, and
said capacitor elements also comprising said capacitor electrode and said second conductive film of said memory cells.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/866,874Filed 15 Jun 2004 · continuation
Priority: JP 6-11492527 May 1994
Published: US 2004/0264274 A130 Dec 2004
Granted: 4 Apr 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

Family

Application08/451,117Parent of this continuation · filed 25 May 1995
Application08/880,736Parent of this division · filed 23 Jun 1997
US 5,754,467 AParent of this continuation · filed 19 May 1998
Application09/334,266Parent of this division · filed 16 Jun 1999
US 5,946,565 AParent of this division · filed 31 Aug 1999
Application09/755,184Parent of this continuation · filed 8 Jan 2001
US 6,211,004 B1Parent of this division · filed 3 Apr 2001
Application10/304,045Parent of this continuation · filed 26 Nov 2002
US 6,548,885 B2Parent of this continuation · filed 15 Apr 2003
US 2004/0264274 A1Pre-grant publication · published 30 Dec 2004
US 6,809,399 B2Parent of this continuation
Application09/755,184Parent of this division
Application08/880,736Parent of this continuation
US 2001/0019641 A1Published application
US 2003/0122159 A1Published application
US 7,023,071 B2This patent

From the US filing history. Foreign family members aren’t listed.

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