Semiconductor device
AssigneeOki Electric Industry Co., Ltd.
InventorKatsuhiro Kato
Life of this patent
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Abstract
The present invention prevents electrostatic discharge damage which may occur when a device chip which has a circuit with fuses mounted thereon is packaged by COG packaging, without increasing an area occupied on the device chip. The height from the chip substrate surface to the top face 138b of the chip terminal 103b formed on the chip substrate surface 136 is formed to be higher than the height from the chip substrate surface to the top face 138a of the fuse terminal 103a. By this, an electrostatic discharge occurs at the chip terminal side when packaged in a COG packaging, so an electrostatic discharge does not occur to the fuse terminal side.
Claims8
A semiconductor device, comprising:
- exposed fuse terminals provided adjacent a chip substrate surface;
- and
- an exposed discharge contribution terminal which is provided adjacent said chip substrate surface;
- wherein a first height, from said chip substrate surface to a top face of said discharge contribution terminal, is higher than a second height, from said chip substrate surface to a top face of said fuse terminals.
A semiconductor device, comprising:
- fuse terminals provided on a chip substrate surface;
- and
- a discharge contribution terminal which is provided at the upper side on said chip substrate surface and of which the height from said chip substrate surface to the top face is higher than the height of the top face of said fuse terminals;
- wherein said discharge contribution terminal is a dummy terminal which is disposed so as to surround the fuse terminals.
Dependencies are inferred from the claim text.