US 7,023,069 B2Granted

Method for forming thick dielectric regions using etched trenches

AssigneeThird Dimension (3D) Semiconductor, Inc.

InventorRichard A. Blanchard

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Abstract

A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The method also includes providing in the semiconductor substrate one or more trenches, first mesas and second mesas. The method also includes oxidizing sidewalls and bottoms of each trench; depositing a doped oxide into each trench and on the tops of the first and second mesas; and thermally oxidizing the semiconductor substrate at a temperature sufficient enough to cause the deposited oxide to flow so that the silicon in each of the first mesas is completely converted to silicon dioxide while the silicon in each of the second mesas is only partially converted to silicon dioxide and so that each of the trenches is filled with oxide.

Claims14

Dependent claims

A method of manufacturing a semiconductor device comprising:

providing a semiconductor substrate having first and second main surfaces opposite to each other, the semiconductor substrate having a heavily doped region of a first or a second conductivity type proximate the second main surface and having a lightly doped region of the first conductivity type proximate the first main surface;
forming in the semiconductor substrate one or more trenches, first mesas and second mesas, each trench being disposed between adjacent mesas and each trench having an approximate equal width along its entire length, the first mesas having a width substantially less than a width of the second mesas;
oxidizing sidewalls and bottoms of each trench;
depositing a doped oxide into each trench and on the tops of the first and second mesas;
and
thermally oxidizing the semiconductor substrate at a temperature sufficient enough to cause the deposited oxide to flow so that the silicon in each of the first mesas is completely converted to silicon dioxide while the silicon in each of the second mesas is only partially converted to silicon dioxide and so that each of the trenches is filled with oxide.

3 more elements

A method of manufacturing a semiconductor device comprising:

providing a semiconductor substrate having first and second main surfaces opposite to each other, the semiconductor substrate having a heavily doped region of a first or second conductivity type proximate the second main surface and having a lightly doped region of the first conductivity type proximate the first main surface;
providing in the semiconductor substrate at least one trench, at least one first mesa and at least one second mesa, the at least one trench being disposed between adjacent mesas, the at least one first mesa having a width substantially less than a width of the at least one second mesa, each mesa having a first extending portion extending from the first main surface toward the heavily doped region to a first depth position, with each trench having an approximate equal width and with each member of the plurality of trenches having approximate equal width and with each mesa region being surrounded by a trench;
implanting a dopant of the second conductivity type into a sidewall surface of each mesa to form at the sidewall surface of each mesa, a first doped region of the second conductivity type having a doping concentration lower than that of the heavily doped region;
oxidizing the bottom of each trench and its sidewalls to create a bottom oxide layer;
depositing an oxide layer using doped silicon dioxide selected from a group consisting of phospho-silicate glass (PSG), boro-silicate glass (BSG) and boro-phospho-silicate glass (BPSG) into each trench;
thermally oxidizing the semiconductor substrate at a temperature sufficiently high to allow the deposited oxide to flow so that the silicon in the at least one first mesa region is completely converted to silicon dioxide while the silicon in the at least one second mesa is only partially converted to silicon dioxide and so each of the trenches is filled with oxide;
and
planarizing the top surface of the semiconductor device.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/004,694Filed 3 Dec 2004 · us provisional application
Priority: 19 Dec 2003
Published: US 2005/0139914 A130 Jun 2005
Granted: 4 Apr 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 30/0291
Of double-diffused metal oxide semiconductor [DMOS] FETs: of vertical dmos [vdmos] fets
H10D 12/032
Of igbts: of vertical IGBTs
H10D 62/111
Reduced surface field [RESURF] PN junction structures: multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
H10D 62/116
Dielectric isolations, e.g. air gaps: adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions