Back to results
US 7,023,068 B1Granted
Method of etching a lateral trench under a drain junction of a MOS transistor
AssigneeNational Semiconductor Corporation
InventorsPeter J. Hopper, Philipp Lindorfer, Vladislav Vashchenho, Peter Johnson
Life of this patent
Estimating the term…
Abstract
In a MOS transistor, the drain capacitance is reduced by forming a lateral trench underneath the drain. This is typically done by using an anisotropic wet etch process in a <110> direction of a <100> orientation wafer.
Claims8
A MOS transistor with reduced drain capacitance comprising
- a drain, and
- a lateral isolation trench extending at least partially underneath the drain, wherein the trench has a <110> orientation.
A method of forming a laterally extending trench in a semiconductor material underneath a drain of a MOS transistor, comprising
- choosing a predetermined crystal orientation,
- etching a vertically extending STI region next to the drain, and
- using an anisotropic etchant to etch a trench extending laterally from the STI, wherein choosing of the crystal orientation includes choosing a lateral trench direction that is in the <110> direction.
Dependencies are inferred from the claim text.