CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding
AssigneeInternational Business Machines Corporation
InventorsMeikei Ieong, Alexander Reznicek, Min Yang
Life of this patent
Estimating the term…
Abstract
A method in which semiconductor-to-semiconductor direct wafer bonding is employed to provide a hybrid substrate having semiconductor layers of different crystallographic orientations that are separated by a conductive or insulating interface is provided. Also provided are the hybrid substrate produced by the method as well as using the direct bonding method to provide an integrated semiconductor structure in which various CMOS devices are built upon a surface orientation that enhances device performance.
Claims17
A hybrid substrate comprising:
- a first region having an upper surface of a second crystallographic orientation comprising a bottom semiconductor layer having a first crystallographic orientation which is different from said second crystallographic orientation and a top semiconductor layer having said second crystallographic orientation, wherein said top and bottom semiconductor layers are vertically separated from each other by a bonding interface, said top semiconductor layer has a thickness from about 200 nm to about 2 μm and said interface has an oxide thickness of about 10 nm or greater;
- and
- a second region having an upper surface of said first crystallographic orientation which is substantially coplanar with said upper surface of said first region, wherein said second region is absent of said bonding interface and comprises said bottom semiconductor layer and an epitaxial semiconductor layer.
An integrated semiconductor structure comprising:
- a hybrid structure comprising a first device region having a first crystallographic orientation and a second device region having a second crystallographic orientation, said first crystallographic orientation is different from said second crystallographic orientation and said first device region is substantially coplanar to said second device region, wherein at least said first device region or said second device region includes an upper semiconductor layer having a thickness from about 200 nm to about 2 μm and an underlying bonding interface that has an oxide thickness of about 10 nm or greater, said underlying bonding interface vertically separating said upper semiconductor layer from a lower semiconductor layer said upper and lower semiconductor layers having different crystallographic orientations and said bonding interface is absent from the other device region;
- an isolation region separating said first device region from said second device region;
- and
- at least one first semiconductor device located in said first device region and at least one second semiconductor device located in said second device region.
Dependencies are inferred from the claim text.