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US 7,023,051 B2Granted
Localized strained semiconductor on insulator
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
Estimating the term…
Abstract
One aspect of this disclosure relates to a method for straining a transistor body region. In various embodiments, oxygen ions are implanted to a predetermined depth in a localized region of a semiconductor substrate, and the substrate is annealed. Oxide growth within the semiconductor substrate forms a local oxide region within the semiconductor substrate. A portion of the substrate forms a semiconductor layer over the local oxide region. In various embodiments, the semiconductor layer is an ultra-thin semiconductor layer having a thickness of approximately 300 Å or less. The oxide growth strains the semiconductor layer. An active region, including the body region, of the transistor is formed in the strained semiconductor layer. Other aspects are provided herein.
Claims25
A transistor structure, comprising:
- a semiconductor substrate;
- a localized insulator region formed within the substrate to partially separate a semiconductor layer from the semiconductor substrate, the semiconductor layer having a strain induced by growth of the insulator region, the strained semiconductor layer having a thickness of approximately 300 Å or less;
- first and second diffusion regions formed in the strained semiconductor layer over the insulator region, the first and second diffusion regions being separated by a body region in the strained semiconductor layer;
- and
- a gate operably positioned over the body region, the gate being separated from the body region by a gate dielectric.
2 more elements
A transistor structure, comprising:
- a silicon substrate;
- a localized buried oxide (BOX) region formed within the silicon substrate to partially separate a silicon layer from the silicon substrate, the silicon layer being positioned over the BOX region, the silicon layer having a strain induced by growth of the BOX region, the strained silicon layer having a thickness of approximately 300 Å or less;
- first and second diffusion regions formed in the strained silicon layer over the BOX region, the first and second diffusion regions being separated by a body region in the strained silicon layer;
- and
- a gate operably positioned over the body region, the gate being separated from the body region by a gate dielectric.
2 more elements
A transistor structure, comprising:
- a silicon substrate;
- a localized buried oxide (BOX) region formed within the silicon substrate to partially separate a silicon layer from the silicon substrate, the silicon layer having a strain induced by growth of the BOX region, the BOX region having a length of approximately 3000 Å and a thickness of approximately 450 Å to strain in the silicon layer with a strain within a range between approximately 1% and approximately 1.2%, the BOX region having a tapered shape such that the strain in the silicon layer is approximately uniform, the strained silicon layer having a thickness of approximately 300 Å or less;
- first and second diffusion regions formed in the strained silicon layer over the BOX region, the first and second diffusion regions being separated by a body region in the strained silicon layer;
- and
- a gate operably positioned over the body region, the gate being separated from the body region by a gate dielectric.
2 more elements
An n-channel CMOS transistor structure, comprising:
- a silicon substrate;
- a localized buried oxide (BOX) region formed within the silicon substrate to partially separate a silicon layer from the silicon substrate, the silicon layer being positioned over the BOX region, the silicon layer having a strain induced by growth of the BOX region, the induced strain being within a range of approximately 0.75% to approximately 1.5%, the strained silicon layer having a thickness of approximately 300 Å or less;
- first and second diffusion regions containing an n+ type dopant formed in the strained silicon layer over the BOX region, the first and second diffusion regions being separated by a body region in the strained silicon layer;
- and
- a gate operably positioned over the body region, the gate being separated from the body region by a gate dielectric.
2 more elements
A memory array, comprising:
- a plurality of memory cells arranged in rows and columns, the memory cells being formed in a semiconductor substrate;
- a plurality of word lines, each word line being connected to a row of memory cells;
- a plurality of bit lines, each bit line being connected to a column of memory cells, wherein each memory cell includes at least one transistor, including:
- a localized insulator region formed within the semiconductor substrate to partially separate a semiconductor layer from the semiconductor substrate, the semiconductor layer having a strain induced by growth of the insulator region, the strained semiconductor layer having a thickness of approximately 300 Å or less;
- first and second diffusion regions formed in the strained semiconductor layer over the insulator region, the first and second diffusion regions being separated by a body region in the strained semiconductor layer;
- and
- a gate operably positioned over the body region, the gate being separated from the body region by a gate dielectric.
4 more elements
A memory device, comprising:
- a memory array formed in a semiconductor substrate, including:
- a plurality of memory cells arranged in rows and columns;
- a plurality of word lines, each word line being connected to a row of memory cells;
- a plurality of bit lines, each bit line being connected to a column of memory cells;
- and
- control circuitry formed in the semiconductor substrate, including word line select circuitry and bit line select circuitry for use in selecting a number of memory cells for writing and reading operations,
- wherein at least one of the memory array and the control circuitry includes at least one transistor, including:
- a localized insulator region formed within the semiconductor substrate to partially separate a semiconductor layer from the semiconductor substrate, the semiconductor layer having a strain induced by growth of the insulator region, the strained semiconductor layer having a thickness of approximately 300 Å or less;
- first and second diffusion regions formed in the strained semiconductor layer over the insulator region, the first and second diffusion regions being separated by a body region in the strained semiconductor layer;
- and
- a gate operably positioned over the body region, the gate being separated from the body region by a gate dielectric.
8 more elements
Dependencies are inferred from the claim text.