MOS device and process for manufacturing MOS devices using dual-polysilicon layer technology

A MOS device comprising

• a passivation layer;
• a stack covered by said passivation layer, said stack comprising a first conductive region, a second conductive region overlying said first conductive region and being separated therefrom by an intermediate dielectric region;
• and
• an electrical connection structure extending through the passivation layer and in direct contact with said first conductive region, second conductive region and said intermediate dielectric region, said electrical connection structure having a substantially constant peripheral shape throughout the entire length of the electrical connection structure.

A MOS device comprising

• a passivation layer;
• a stack covered by said passivation layer, said stack comprising a first conductive region, a second conductive region overlying said first conductive region and being separated therefrom by an intermediate dielectric region;
• and
• an electrical connection region in direct contact with said first conductive region, second conductive region and said intermediate dielectric region, wherein the electrical connection region is an elongated structure substantially free of steps and is formed using a single mask to from portions of the electrical connection region that extends through the passivation layer, second conductive region and intermediate dielectric layer.