DRAM technology compatible processor/memory chips

An integrated circuit formed in and on a semiconductor layer, the integrated circuit comprising:

• a plurality of metal oxide semiconductor field effect transistors (MOSFETs) formed in and on the semiconductor layer;
• a plurality of stacked capacitors disposed above the plurality of MOSFETs, each of the stacked capacitors providing a coupling ratio greater than 1.0;
• an insulator layer separating the plurality of stacked capacitors from the plurality of MOSFETs;
• wherein a first group of the plurality of stacked capacitors is selectively coupled to gates of the MOSFETs to form non-volatile memory cells for a first sub-circuit;
• wherein a second group of the plurality of stacked capacitors is selectively coupled to diffused regions of the MOSFETs to form a second sub-circuit;
• and
• wherein the first sub-circuit is operatively coupled to the second sub-circuit.

An integrated circuit formed in and on a semiconductor layer, the integrated circuit comprising:

• a plurality of metal oxide semiconductor field effect transistors (MOSFETs) formed in and on the semiconductor layer, each of the MOSFETs including a channel region, a gate oxide on the channel region, and a gate on the gate oxide, wherein the gate oxide is a tunneling oxide;
• a plurality of stacked capacitors disposed above the plurality of MOSFETs, each of the stacked capacitors providing a coupling ratio greater than 1.0;
• an insulator layer separating the plurality of stacked capacitors from the plurality of MOSFETs;
• wherein a first group of the plurality of stacked capacitors is selectively coupled to gates of the MOSFETs to form non-volatile memory cells for a first sub-circuit;
• wherein a second group of the plurality of stacked capacitors is selectively coupled to diffused regions of the MOSFETs to form a second sub-circuit;
• and
• wherein the first sub-circuit is operatively coupled to the second sub-circuit.

An integrated circuit formed in and on a semiconductor layer, the integrated circuit comprising:

• a plurality of metal oxide semiconductor field effect transistors (MOSFETs) formed in and on the semiconductor layer, each of the MOSFETs including a channel region, a gate oxide on the channel region, and a gate on the gate oxide, wherein the gate oxide has a thickness of less than 100 Angstroms;
• a plurality of stacked capacitors disposed above the plurality of MOSFETs, each of the stacked capacitors providing a coupling ratio greater than 1.0;
• an insulator layer separating the plurality of stacked capacitors from the plurality of MOSFETs;
• wherein a first group of the plurality of stacked capacitors is selectively coupled to gates of the MOSFETS to form non-volatile memory cells for a first sub-circuit;
• wherein a second group of the plurality of stacked capacitors is selectively coupled to diffused regions of the MOSFETs to form a second sub-circuit;
• and
• wherein the first sub-circuit is operatively coupled to the second sub-circuit.

An integrated circuit formed in and on a semiconductor layer, the integrated circuit comprising:

• a plurality of metal oxide semiconductor field effect transistors (MOSFETs) formed in and on the semiconductor layer, each of the MOSFETs including a channel region, a gate oxide on the channel region, and a gate on the gate oxide, wherein the gate oxide is adapted to act as a tunneling oxide and has a thickness of less than 100 Angstroms;
• a plurality of stacked capacitors disposed above the plurality of MOSFETs;
• an insulator layer separating the plurality of stacked capacitors from the plurality of MOSFETs;
• wherein a first group of the plurality of stacked capacitors is selectively coupled to gates of the MOSFETs to form non-volatile memory cells for a first sub-circuit;
• wherein a second group of the plurality of stacked capacitors is selectively coupled to diffused regions of the MOSFETs to form a second sub-circuit;
• and
• wherein the first sub-circuit is operatively coupled to the second sub-circuit.