Lateral junction field-effect transistor

A lateral junction field-effect transistor comprising:

• a first semiconductor layer (2) placed on a semiconductor substrate (1) and containing impurities of a first conductivity type (p);
• a second semiconductor layer (3) placed on said first semiconductor layer (2) and containing impurities of a second conductivity type (n) with a higher impurity concentration than that of said first semiconductor layer (2);
• a third semiconductor layer (6) placed on said second semiconductor layer (3) and containing impurities of the first conductivity type (p);
• source/drain region layers (5, 9) spaced from each other by a predetermined distance in said third semiconductor layer (6) and containing impurities of the second conductivity type (n) with a higher impurity concentration than that of said second semiconductor layer (3);
• a gate region layer (7) provided between said source/drain region layers (5, 9) in said third semiconductor layer (6), having its bottom surface extending into said second semiconductor layer (3) and containing impurities of the first conductivity type (p) with a higher impurity concentration than that of said second semiconductor layer (3);
• and
• an impurity injection region (17, 17a, 17b) provided in said second semiconductor layer (3) between said first semiconductor layer (2) and said gate region layer (7), said impurity injection region having substantially the same impurity concentration and the same potential as those of said gate region layer (7).