MOS transistor with serrated gate structures
AssigneeNational Semiconductor Corporation
InventorsJames Thomas Doyle, Michael Angelo Tamburrino
Life of this patent
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Abstract
A digital power supply system provides a supply voltage to semiconductor circuits. The power supply system utilizes a pulse width modulator to output a signal into a LC filter that generates a DC supply voltage. The width of the pulses output by the pulse width modulator are defined by an encoder that generates width information in response to a propagation delay detector that measures the propagation delay of a first clock signal when clocked by a second clock signal.
Claims16
A MOS transistor formed in a semiconductor material of a first conductivity type, the MOS transistor comprising:
- a plurality of source strips of a second conductivity type formed in the semiconductor material, each source strip having a depth, a length, and a width;
- a plurality of drain strips of the second conductivity type formed in the semiconductor material such that a drain strip lies between each adjacent pair of source strips, each drain strip having the depth, the length, and a width;
- a plurality of channel strips located between the source and drain strips such that a channel strip is located between each adjacent source and drain strip;
- a plurality of gate strips formed over the channel strips between source strips and drain strips, the plurality of gate strips being isolated from the plurality of channel strips;
- and
- a single source metal region formed over the plurality of source and drain strips to make electrical connections with the plurality of source strips, the single source metal region covering more than 25% and less than 50% of the plurality of source and drain strips.
A MOS transistor formed in a semiconductor material of a first conductivity type, the MOS transistor comprising:
- a plurality of source strips of a second conductivity type formed in the semiconductor material, each source strip having a depth, a length, and a width;
- a plurality of drain strips of the second conductivity type formed in the semiconductor material such that a drain strip lies between each adjacent pair of source strips, each drain strip having the depth, the length, and a width, the width of a source strip being greater than a width of a drain strip;
- a plurality of channel strips located between the source and drain strips such that a channel strip is located between each adjacent source and drain strip;
- and
- a plurality of gate strips formed over the channel strips between source strips and drain strips, the plurality of gate strips being isolated from the plurality of channel strips.
Dependencies are inferred from the claim text.