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US 7,023,031 B2Granted
CMOS imager having on-chip ROM
AssigneeMicron Technology, Inc.
InventorRichard H. Tsai
Life of this patent
Estimating the term…
Abstract
A CMOS image sensor formed on a chip has a ROM disposed on the chip for recording pixel defect locations, chip-by-chip variations such as bias, and other manufacturing production data. Testing results and repair solutions are written to the ROM after production testing. A simple circuit for writing information to the ROM also is provided on the CMOS chip. During operational use of the image sensor, data is read from the on-chip ROM to assist in compensating for manufacturing process variations.
Claims20
An imaging system comprising:
- a chip having a sensor array including a plurality of pixels which provide respective signals representative of light incident upon the sensor array;
- and
- a programmable non-volatile memory located on the chip to store information associated with the sensor array, said memory including:
- rows and columns of addressable fuses connected between a respective pair of row and column lines, each row line being connected to a single respective row access transistor;
- a first column access transistor coupled by a source/drain connection to each respective column line;
- a second column access transistor coupled by a source/drain connection to each respective column line;
- and
- a control circuit arranged and configured to selectively operate said row and first column transistors to provide a voltage at a first level through a respective row access transistor, a respective first column access transistor, and across a selected fuse sufficient to break the link during a programming operation and for selectively operating said row and first column access transistors to provide a voltage of a second level lower than the first level through the respective row access transistor, a respective second column access transistor, and across the selected fuse link during a read operation.
5 more elements
An integrated circuit comprising:
- an image sensor for outputting signals representative of input light;
- a programmable non-volatile memory for storing image sensor information;
- and
- a controller for interfacing with the programmable non-volatile memory and accessing the image sensor information, wherein the non-volatile memory includes:
- a row and column array of individually-addressable fuses, each fuse being connected between a respective pair of row and column lines, each row line being connected to a single respective pair of row and column lines, each row line being connected to a single respective row access transistor;
- a read column transistor coupled by a source/drain connection respectively to each column line of the array,
- a programming column transistor coupled by a source/drain connection respectively to each column line of the array;
- a programming circuit operating said row and column transistors to provide a voltage at a first level through a respective row access transistor and a respective read column transistor, and across a selected fuse during a read operation and a voltage of a second level higher than the first through a respective row access transistor and a selected programming column transistor, and across a selected fuse link, the voltage of the second level being sufficient to break the link during a programming operation.
5 more elements
A method of operating an image sensor, the method comprising
- obtaining at least one of manufacturing and testing information for an image sensor fabricated on a semiconductor chip;
- storing the information in a programmable non-volatile memory, made up of a row and column array of individually-addressable fuses fabricated on said chips, by accessing a selected row of the array by way of a row access transistor coupled respectively to said selected row and a selected column of the array by way of a column programming transistor coupled by a source/drain connection respectively to said selected column of the array, and selectively applying a programming potential through a respective row access transistor and a respective column programming transistor across a fuse using the selected row and column which is sufficient to break the selected fuse link for storing information in the memory;
- and
- reading the information stored in the memory by accessing the selected column by way of a read transistor coupled by a source/drain connection respectively to said selected column and accessing a selected row by way of the row access transistor and applying a read potential lower than the programming potential through the row access transistor and the read transistor, and across a fuse defined by the selected row and column, the read potential being insufficient to break the fuse.
1 more element
An image sensing device comprising:
- an array of CMOS pixels fabricated on a chip;
- a programmable read-only memory fabricated on the chip, the read-only memory including a row and column array of fuses, each row being connected to a single respective row access transistor;
- a column programming transistor coupled by a source/drain connection respectively to each column of the array of fuses, a selected column programming transistor being used with a selected row access transistor to provide a potential through the selected row access transistor sufficient to break a fuse link associated with the selected row and column;
- a column read transistor coupled by a source/drain connection respectively to each column of the array of fuses, a selected column read transistor being used with the selected row access transistor to provide a read potential lower than the programming potential through the selected row access transistor and the column read transistor to a fuse defined by a selected row and column, the read potential being insufficient to break the respective fuse;
- and
- access circuitry for writing and reading information to and from the read only memory.
3 more elements
Dependencies are inferred from the claim text.