Misfet
AssigneeQuantum Semiconductor LLC
InventorCarlos Augusto
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AssigneeQuantum Semiconductor LLC
InventorCarlos Augusto
Estimating the term…
A metal insulator semiconductor field effect transistor (MISFET) is disclosed comprising a source layer being made with a material having a source band-gap (EG2) and a source mid-gap value (EGM2), the source layer having a source Fermi-Level (EF2). A drain layer has a drain Fermi-Level (EF4). A channel layer is provided between the source layer and the drain layer, the channel layer being made with a material having a channel band-gap (EG3) and a channel mid-gap value (EGM3), the channel layer having a channel Fermi-Level (EF3). A source contact layer is connected to the source layer opposite the channel layer, the source contact layer having a source contact Fermi-Level (EF1). A gate electrode has a gate electrode Fermi-Level (EF6). The source band-gap is substantially narrower (EG2) than the channel band-gap (EG3). The source contact Fermi-Level (EF1), the source Fermi-Level (EF2), the channel Fermi-Level (EF3), the drain Fermi-Level (EF4) and the gate electrode Fermi-Level (EF6) are equal to the source mid-gap value (EGM2) and the channel mid-gap value (EGM3), within a predetermined tolerance value, when no voltage is applied to the device.
A device comprising a drain, a gate, a channel, and a source, having sufficiently symmetric paths from source to drain for electrons and for holes such that the device acts like a NMOS when drain to source (VDS) and gate to source (VGS) voltages are positive, and acts like a PMOS when drain to source (VDS) and gate to source (VDS) voltages are negative, and wherein a source to channel barrier height can be modulated by a field-effect, and a channel to drain barrier height is not affected by gate bias.
A device comprising a drain, a source, channel, gate(s), and source, gate, and drain electrodes, wherein:
A device comprising a drain, a source, channel, and gate(s) wherein:
Dependencies are inferred from the claim text.