SiGe transistor with strained layers

A P-type Metal Oxide Semiconductor (PMOS) device, comprising:

• a tensile-strained silicon layer located on a silicon-germanium substrate;
• silicon-germanium source/drain structures on or in said tensile-strained silicon layer, wherein said silicon-germanium source/drain structures comprise an alloy having between about 30 and about 50 atom percent germanium;
• and
• a channel region located between said silicon-germanium source/drain structures and within said tensile-stained silicon layer, said channel region further having a compressive stress in a direction parallel to an intended current flow through said channel region.

A Metal Oxide Semiconductor (MOS) device, including:

• a P-type Metal Oxide Semiconductor (PMOS) transistor, comprising:
• a tensile-strained silicon layer located on a silicon-germanium substrate;
• p-doped silicon-germanium source/drain structures on or in said tensile-strained silicon layer;
• and
• an n-type channel region located between said p-doped silicon-germanium source/drain structures and within said tensile-strained silicon layer, said n-type channel region further having a compressive stress in a direction parallel to an intended current flow through said n-type channel region,
• wherein said compressive stress is substantially equal to or greater in magnitude than a tensile stress of said tensile-stained silicon layer in said direction;
• and
• an N-type metal Oxide Semiconductor (NMOS) transistor, comprising:
• n-doped source/drain structures located in or on said tensile-strained silicon layer;
• and
• a p-type channel region located between said n-doped source/drain structures and within said tensile-strained silicon layer, said p-type channel having a tensile strain in directions parallel and perpendicular to an intended current flow through said p-type channel region.