Method of forming ultra shallow junctions
AssigneeSilTerra Malaysia Sdn. Bhd.
InventorNarayanan Meyyappan
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Abstract
The present invention relates to a method of fabricating a semiconductor device. In specific embodiments, the method comprises providing a semiconductor substrate, and ion implanting dopant impurities over a time period into the semiconductor device by varying an ion energy of implanting the dopant impurities over the time period. The dopant impurities are activation annealed to form one or more doped regions extending below the surface of the semiconductor substrate. The ion energy may be varied continuously or in a stepwise manner over the time period, and may also be varied in a cyclical manner.
Claims12
A method of fabricating a semiconductor device, the method comprising:
- providing a semiconductor substrate defining a gate structure and first and second regions, each region being provided on one side the gate structure;
- ion implanting dopant impurities over a first time period into the first and second regions of the semiconductor device with a first ion energy of implanting the dopant impurities over the first time period;
- ion implanting the dopant impurities over a second time period into the first and second regions of the semiconductor device with a second ion energy of implanting the dopant impurities over the second time period;
- ion implanting the dopant impurities over a third time period into the first and second regions of the semiconductor device with a third ion energy of implanting the dopant impurities over the third time period;
- and
- activation annealing the dopant impurities to form at least one doped region extending below the surface of the semiconductor substrate,
- wherein the three separate ion-implantation steps are performed to provide the first and second regions with ultra shallow junctions.
A method of fabricating a semiconductor device, the method comprising:
- providing a silicon substrate having a gate electrode and a gate oxide layer disposed thereon;
- ion implanting dopant impurities over a time period in the semiconductor device by varying an ion energy of implanting the dopant impurities over the time period, wherein the lateral coverage of the dopant impurities implanted into the substrate remain substantially the same while the ion implantation energy is varied over time;
- and
- activation annealing the dopant impurities to form doped source/drain regions extending below the surface of the silicon substrate on opposite sides of the gate electrode and gate oxide layer disposed thereon;
- wherein the ion energy is varied in a sawtooth manner over the time period.
Dependencies are inferred from the claim text.