Method to manufacture high voltage MOS transistor by ion implantation
AssigneeInfineon Technologies AG
InventorPeter Olofsson
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Abstract
A method for fabrication of a high-voltage, high-frequency MOS-transistor combines a deep n-well and a p-well process and the formation of an extended drain region (45), and a channel region (31), the channel having a short length and becoming well aligned with the gate edge. The deep n-well (11) and the p-well (19) are both produced by ion implantation. The method is compatible with a standard CMOS process and gives low manufacturing costs, increased breakdown voltage, better overall high-frequency performance, and the prevention of the “body effect” occurring by isolation of the p-well.
Claims20
A method of manufacturing a high voltage, high speed MOS transistor, comprising the steps of:
- forming in a semiconductor substrate of a first conductivity type a buried first well region of a second conductivity type, wherein the first well region is formed by high energy implantation to locate the first well region deep within the substrate,
- forming a second well region of the first conductivity type between the surface of the substrate and the first well region, wherein the second well region is formed by high energy implantation to locate the second well region between the surface of the substrate and the first well region,
- forming channel areas of the first conductivity type by ion implantation inside the second well region,
- forming gate regions on the surface of the substrate,
- forming a weakly doped extended drain region by ion implantation inside the second well region,
- forming source, drain and sinker regions having a heavy doping of the second conductivity type, the source regions being formed within the channel areas, and
- forming contact plugs of the second conductivity type extending from the surface of the substrate to the first well region by ion implantation.
A method of manufacturing a high voltage, high speed MOS transistor, comprising the steps of:
- forming in a semiconductor substrate of a first conductivity type a buried first well region of a second conductivity type, wherein the first well region is formed by ion implantation of phosphorus to locate the first well region deep within the substrate,
- forming a second well region of the first conductivity type between the surface of the substrate and the first well region, wherein the second well region is formed by ion implantation of boron to locate the second well region between the surface of the substrate and the first well region,
- forming channel areas of the first conductivity type by ion implantation inside the second well region,
- forming gate regions on the surface of the substrate,
- forming a weakly doped extended drain region by ion implantation inside the second well region,
- forming source, drain and sinker regions having a heavy doping of the second conductivity type, the source regions being formed within the channel areas, and
- forming contact plugs of the second conductivity type extending from the surface of the substrate to the first well region by ion implantation.
Dependencies are inferred from the claim text.