US 7,018,921 B2Granted

Method of forming metal line in semiconductor device

AssigneeHynix Semiconductor Inc.

InventorSang Wook Ryu

Life of this patent

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Abstract

The present invention relates to a method of forming a metal line in a semiconductor device, in which an etch-stopping layer is deposited between the interlayer insulation films and then over-etching is performed by using the etch-stopping layer as an etching barrier during the etching process for forming the subsequent trenches. Therefore, it is possible to restrain occurrence of parasitic spacers in the trenches.

Claims4

Dependent claims

A method of forming a metal line in a semiconductor device, comprising:

(a) sequentially forming a first interlayer insulation film, an etch-stopping layer, and a second interlayer insulation film on a semiconductor substrate having a predetermined semiconductor structural layer;
(b) forming a contact hole which partially exposes the semiconductor structural layer by performing an etching process using an etching mask for the contact hole;
(c) forming a metal plug to bury the contact hole;
(d) sequentially forming an anti-diffusion film and a third interlayer insulation film on the semiconductor device including the metal plug;
(e) performing an etching process using an etching mask for a trench to form the trench in such a way that the second interlayer insulation film is over-etched by using the etch-stopping layer as an etching barrier;
and
(f) forming a metal line to bury the trench.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/724,093Filed 1 Dec 2003
Priority: KR 10-2003-004711711 Jul 2003
Published: US 2005/0009321 A113 Jan 2005
Granted: 28 Mar 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10W 20/077
Of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers: on sidewalls or on…
H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10W 20/074
Of dielectric parts thereof: of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or…
H10W 20/081
Of dielectric parts thereof: by forming openings in the dielectric parts

Family

US 2005/0009321 A1Pre-grant publication · published 13 Jan 2005
US 7,018,921 B2This patent

From the US filing history. Foreign family members aren’t listed.

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Abstract

Facts

Application

10/724,093Filed 1 Dec 2003

Priority

KR 10-2003-004711711 Jul 2003

Published

US 2005/0009321 A113 Jan 2005

Granted

28 Mar 2006

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10W 20/077
Of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers: on sidewalls or on…
H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10W 20/074
Of dielectric parts thereof: of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or…
H10W 20/081
Of dielectric parts thereof: by forming openings in the dielectric parts