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US 7,018,917 B2Granted
Multilayer metallization
AssigneeASM International N.V.
InventorKai-Erik Elers
Life of this patent
Estimating the term…
Abstract
Multiple metallization layers in a partially fabricated integrated circuit are formed in a single process step. As a place-holder for the later-deposited metallization layers, sacrificial material is deposited in the integrated circuit at desired locations at various fabrication levels over a substrate. The sacrificial material is then removed to form a contiguous open volume spanning multiple fabrication levels. A conductor is then deposited in the open volume to form multiple metallization layers in a single step.
Claims38
A process for forming a conductive element, comprising:
- providing a semiconductor substrate;
- depositing a sacrificial material over the substrate, wherein the sacrificial material comprises a metal or an organic material;
- forming an insulating layer over the sacrificial material;
- forming an opening through the insulating layer to partially expose the sacrificial material;
- selectively removing the sacrificial material to form a buried open volume;
- and
- simultaneously depositing a conductor in the buried open volume and the opening to form the conductive element.
4 more elements
A process for forming a conductive element comprising:
- providing a semiconductor substrate;
- depositing a sacrificial material over the substrate, wherein the sacrificial material comprises a material that can be sublimed below about 400° C.;
- forming an insulating layer over the sacrificial material;
- forming an opening through the insulating layer to partially expose the sacrificial material;
- selectively removing the sacrificial material to form a buried open volume;
- and
- simultaneously depositing a conductor in the buried open volume and the opening to form the conductive element.
4 more elements
A method of semiconductor processing, comprising:
- providing a partially fabricated integrated circuit having a top surface and a generally vertical opening leading to a buried open volume, wherein the buried open volume extends laterally beneath the top surface;
- and
- forming a conductive line under the top surface by substantially filling the buried open volume with a conductor, wherein forming a conductive line comprises depositing a metal selected from the group consisting of copper, silver and gold.
A method of semiconductor processing, comprising:
- providing a partially fabricated integrated circuit having a top surface and a generally vertical opening leading to a buried open volume, wherein the buried open volume extends laterally beneath the top surface;
- and
- forming a conductive line under the top surface by substantially filling the buried open volume with a conductor, wherein substantially filling the open volume comprises depositing the conductor by atomic layer deposition.
A method of semiconductor processing, comprising:
- providing a partially fabricated integrated circuit having a top surface and a generally vertical opening leading to a buried open volume, wherein the buried open volume extends laterally beneath the top surface;
- and
- forming a conductive line under the top surface by substantially filling the buried open volume with a conductor, wherein forming a conductive line comprises filling the open volume with a conductive polymer.
A method of semiconductor processing, comprising:
- providing a partially fabricated integrated circuit having a top surface and a generally vertical opening leading to a buried open volume, wherein the buried open volume extends laterally beneath the top surface;
- and
- forming a conductive line under the top surface by substantially filling the buried open volume with a conductor, wherein forming a conductive line comprises forming a wire comprising carbon nanotube bits, wherein forming the wire comprises:
- suspending the carbon nanotube bits in a supercritical fluid to form a carbon nanotube mixture;
- introducing the mixture into the open volume;
- removing the supercritical fluid by vaporization;
- and
- applying a weak electric field to join the carbon nanotube bits together.
5 more elements
A method of semiconductor processing, comprising:
- providing a partially fabricated integrated circuit having a top surface and a generally vertical opening leading to a buried open volume, wherein the buried open volume extends laterally beneath the top surface;
- and
- forming a conductive line under the top surface by substantially filling the buried open volume with a conductor, wherein forming a conductive line comprises:
- forming a nanometal slurry by suspending a nanometal powder in a supercritical fluid;
- introducing the slurry into the open volume;
- removing the supercritical fluid by decreasing a pressure of an ambient atmosphere of the partially fabricated integrated circuit;
- subsequently sintering the nanometal powder by heating the partially fabricated integrated circuit to a temperature between about 200° C. and about 300° C.
4 more elements
A method of semiconductor processing, comprising:
- providing a partially fabricated integrated circuit having a top surface and a generally vertical opening leading to a buried open volume, wherein the buried open volume extends laterally beneath the top surface;
- and
- forming a conductive line under the top surface by substantially filling the buried open volume with a conductor, wherein the conductor comprises polaron threads.
A method of semiconductor processing, comprising:
- providing a semiconductor wafer having a sacrificial material, wherein the sacrificial material extends horizontally underneath a top surface of the wafer;
- removing the sacrificial material to form an opening, wherein the opening spans more than one fabrication level;
- and
- depositing at least one monolayer of a material within the opening, wherein a cross-sectional area of the opening increases with decreasing distance to the top surface.
1 more element
Dependencies are inferred from the claim text.