Method of enlarging contact area of a gate electrode, semiconductor device having a surface-enlarged gate electrode, and method of manufacturing the same

A method of fabricating a semiconductor device, comprising:

• forming a first insulating layer on a substrate, subsequently coating the substrate with a conductive material, and patterning the conductive material to form at least one gate pattern insulated from the substrate by the first insulating layer;
• forming a second insulating layer on the gate pattern and the substrate;
• removing some of the second insulating layer until an upper surface thereof is below a level of an upper surface of the gate pattern;
• forming a second conductive layer comprising the conductive material on the second insulating layer and the gate pattern;
• selectively removing portions of the second conductive layer such that the second insulating layer is exposed, so that a first spacer of the conductive material is formed at both sides of an upper portion of the gate pattern, and a surface area of the gate pattern is enlarged;
• subsequently removing the second insulating layer except at portions adjacent both sides of a lower portion of the gate pattern;
• subsequently implanting ions, at a relatively low concentration, into the substrate at both sides of the gate pattern using the gate pattern as a mask, to thereby form a lightly doped source/drain region on the substrate;
• subsequently forming a fourth insulating layer on the substrate including the gate pattern;
• selectively removing portions of the fourth insulating layer to thereby form a second spacer at the sides of the gate pattern;
• subsequently implanting ions, at a concentration higher than that of said relatively low concentration, into the substrate corresponding at both sides of the gate pattern using the gate pattern and the second spacer as a mask, to thereby form a heavily doped source/drain region on the substrate;
• subsequently performing a heat treatment on the substrate;
• and
• forming a third conductive layer on the gate pattern and on the heavily-doped source/drain region.