Back to results
US 7,018,897 B2Granted
Self aligned method of forming a semiconductor memory array of floating gate memory cells with control gate spacers
AssigneeSilicon Storage Technology, Inc.
InventorChih Hsin Wang
Life of this patent
Estimating the term…
Abstract
A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates are formed in each of the active regions by forming a conductive layer of material. Trenches are formed in the row direction across the active regions, and are filled with a conductive material to form blocks of conductive material that are the control gates. Sidewall spacers of conductive material are formed along the floating gate blocks to give the floating gates protruding portions that extend over the floating gate.
Claims80
A self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, each memory cell having a floating gate, a first terminal, a second terminal with a channel region therebetween, and a control gate, the method comprising:
- a) forming a plurality of spaced apart isolation regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, the active regions each comprising a first layer of insulation material on the semiconductor substrate and a first layer of conductive material on the first layer of insulation material;
- b) forming a plurality of spaced apart first trenches across the active regions and isolation regions which are substantially parallel to one another and extend in a second direction that is substantially perpendicular to the first direction;
- each of the first trenches being substantially rectangularly shaped and exposing the first layer of the conductive material in each of the active regions;
- c) forming a second layer of insulation material in each of the active regions that is disposed adjacent to and over the first layer of conductive material;
- d) filling each of the first trenches with a second conductive material to form blocks of the second conductive material having a substantially rectangular shape, wherein for each of the active regions, each of the blocks is adjacent to the second layer of insulation material and is insulated from the substrate;
- e) forming a sidewall spacer of a conductive material immediately adjacent to and contiguous with each of the blocks along the second direction, wherein for each active region each spacer is disposed over the second layer of insulation material and the first layer of conductive material;
- f) forming a plurality of first terminals in the substrate, wherein in each of the active regions each of the first terminals is adjacent to one of the blocks;
- and
- g) forming a plurality of second terminals in the substrate, wherein in each of the active regions each of the second terminals is spaced apart from the first terminals and is below the first layer of conductive material.
6 more elements
A self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, each memory cell having a floating gate, a first terminal, a second terminal with a channel region therebetween, and a control gate, the method comprising:
- a) forming a plurality of spaced apart isolation regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
- b) forming a plurality of spaced apart first trenches across the active regions and isolation regions which are substantially parallel to one another and extend in a second direction that is substantially perpendicular to the first direction, each of the first trenches being substantially rectangularly shaped, and forming a first layer of conductive material in each of the active regions adjacent to the first trenches and disposed over a first layer of insulation material;
- c) forming a second layer of insulation material in each of the active regions that is disposed adjacent to and over the first layer of conductive material;
- d) filling each of the first trenches with a second conductive material to form blocks of the second conductive material having a substantially rectangular shape, wherein for each of the active regions, each of the blocks is adjacent to the second layer of insulation material and is insulated from the substrate;
- e) forming a sidewall spacer of a conductive material immediately adjacent to and contiguous with each of the blocks along the second direction, wherein for each active region each spacer is disposed over the second layer of insulation material and the first layer of conductive material;
- f) forming a plurality of first terminals in the substrate, wherein in each of the active regions each of the first terminals is adjacent to one of the blocks;
- and
- g) forming a plurality of second terminals in the substrate, wherein in each of the active regions each of the second terminals is spaced apart from the first terminals and is below the first layer of conductive material.
5 more elements
A self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, each memory cell having a floating gate, a first terminal, a second terminal with a channel region therebetween, and a control gate, the method comprising:
- a) forming a plurality of spaced apart isolation regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, the active regions each comprising a first layer of insulation material on the semiconductor substrate and a first layer of conductive material on the first layer of insulation material;
- b) forming a plurality of spaced apart first trenches across the active regions and isolation regions which are substantially parallel to one another and extend in a second direction that is substantially perpendicular to the first direction;
- each of the first trenches exposing the first layer of the conductive material in each of the active regions;
- c) forming a second layer of insulation material in each of the active regions that is disposed adjacent to and over the first layer of conductive material;
- d) filling each of the first trenches with a second conductive material to form blocks of the second conductive material each having a substantially planar sidewall portion, wherein for each of the active regions, each of the blocks is adjacent to the second layer of insulation material and is insulated from the substrate;
- e) forming a sidewall spacer of a conductive material immediately adjacent to and contiguous with each of the substantially planar sidewall portions along the second direction, wherein for each active region each spacer is disposed over the second layer of insulation material and the first layer of conductive material;
- f) forming a plurality of first terminals in the substrate, wherein in each of the active regions each of the first terminals is adjacent to one of the blocks;
- and
- g) forming a plurality of second terminals in the substrate, wherein in each of the active regions each of the second terminals is spaced apart from the first terminals and is below the first layer of conductive material.
6 more elements
A self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, each memory cell having a floating gate, a first terminal, a second terminal with a channel region therebetween, and a control gate, the method comprising:
- a) forming a plurality of spaced apart isolation regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
- b) forming a plurality of spaced apart first trenches across the active regions and isolation regions which are substantially parallel to one another and extend in a second direction that is substantially perpendicular to the first direction, and forming a first layer of conductive material in each of the active regions adjacent to the first trenches and disposed over a first layer of insulation material;
- c) forming a second layer of insulation material in each of the active regions that is disposed adjacent to and over the first layer of conductive material;
- d) filling each of the first trenches with a second conductive material to form blocks of the second conductive material each having a substantially planar sidewall portion, wherein for each of the active regions, each of the blocks is adjacent to the second layer of insulation material and is insulated from the substrate;
- e) forming a sidewall spacer of a conductive material immediately adjacent to and contiguous with each of the substantially planar sidewall portions along the second direction, wherein for each active region each spacer is disposed over the second layer of insulation material and the first layer of conductive material;
- f) forming a plurality of first terminals in the substrate, wherein in each of the active regions each of the first terminals is adjacent to one of the blocks;
- and
- g) forming a plurality of second terminals in the substrate, wherein in each of the active regions each of the second terminals is spaced apart from the first terminals and is below the first layer of conductive material.
5 more elements
Dependencies are inferred from the claim text.