Semiconductor capacitor structure and method for manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsWoo-Gwan Shim, Chang-Ki Hong, Sang-Jun Choi, Jeong-Nam Han
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Abstract
In one embodiment, a semiconductor device comprises a base and a tapered wall formed on the base. The wall has a midline and also has an inner sidewall and an outer sidewall. The inner sidewall and the outer sidewall are substantially symmetrical with each other in relation to the midline. Thus, the reliability of the semiconductor capacitor structure can be improved and the throughput can be increased. Also, further scaling down of semiconductor devices can be facilitated with the principles of the present invention.
Claims30
A method for forming a semiconductor device, the method comprising:
- forming an interlayer insulating layer on a semiconductor substrate, the interlayer insulating layer having a conductive pad therein;
- forming an etch stop layer on the interlayer insulating layer;
- forming a first sacrificial layer on the etch stop layer;
- forming a storage node opening in the first sacrificial layer;
- depositing a conductive layer on the first sacrificial layer and on the sidewalls and the bottom of the opening;
- forming a second sacrificial layer on the conductive layer;
- planarizing the resulting stucture until the top surface of the first sacrificial layer is exposed;
- partially removing an upper portion of the first and second sacrificial layers to expose a sidewall portion of the conductive layer;
- thinning the exposed sidewall portion;
- and
- removing the remaining portion of the first and second sacrificial layers.
A method for forming a semiconductor device, the method comprising:
- forming an interlayer insulating layer on a semiconductor substrate, the interlayer insulating layer having a conductive pad therein;
- forming an etch stop layer on the interlayer insulating layer;
- forming a first sacrificial layer on the etch stop layer;
- forming a storage node opening in the first sacrificial layer;
- depositing a conductive layer on the first sacrificial layer and on the sidewalls and the bottom of the opening;
- forming a second sacrificial layer on the conductive layer;
- planarizing the resulting structure until the top surface of the first sacrificial layer is exposed;
- partially removing the first and second sacrificial layers in a vertical direction to expose inner and outer sidewalls of the planarized conductive layer;
- partially removing the inner and outer sidewalls of the partially exposed conductive layer in a horizontal direction;
- and
- removing the remaining portion of the first and second sacrificial layers.
A method forming a semiconductor device, the method comprising:
- forming an interlayer insulating layer on a semiconductor substrate, the interlayer insulating layer having a conductive pad therein;
- forming an etch stop layer on the interlayer insulating layer;
- forming a first sacrificial layer on the etch stop layer;
- forming a first storage node opening in the first sacrificial layer;
- depositing a conductive layer on the first sacrificial layer and on the sidewalls and the bottom of the opening;
- forming a second sacrificial layer on the conductive layer;
- planarizing the resulting structure until the top surface of the first sacrificial layer is exposed to form a storage node;
- concurrently performing vertical and horizontal etching on the resulting structure such that a width of the storage node is gradually reduced from a bottom to a top of the storage node;
- and
- removing the remaining portion of the first and second sacrificial layers.
Dependencies are inferred from the claim text.