Ultra-thin Si channel CMOS with improved series resistance
AssigneeInternational Business Machines Corporation
InventorsBruce B. Doris, MeiKei Ieong, Thomas S. Kanarsky
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Abstract
Thin silicon channel SOI devices provide the advantage of sharper sub-threshold slope, high mobility, and better short-channel effect control but exhibit a typical disadvantage of increased series resistance. This high series resistance is avoided by using a raised source-drain (RSD), and expanding the source drain on the pFET transistor in the CMOS pair using selective epitaxial Si growth which is decoupled between nFETs and pFETs. By doing so, the series resistance is improved, the extensions are implanted after RSD formation and thus not exposed to the high thermal budget of the RSD process while the pFET and nFET can achieve independent effective offsets.
Claims8
A method of improving the performance of different semiconductor conductivities on the same wafer comprising steps of
- fabricating thin spacers on a wafer adjacent a gate structure,
- depositing a hard mask film across said wafer,
- forming a block mask over a first transistor,
- removing said hard mask film from a second transistor,
- forming a raised source-drain region by selective epitaxy,
- removing said block mask over said first transistor,
- performing additional selective epitaxial growth, effecting only the areas of said second transistor as said hard mask film covering said first transistor is resistant to said additional epitaxial procedure, and
- performing extension implants to RSD regions of at least one of said first or second transistor.
Dependencies are inferred from the claim text.