Method to form local “silicon-on-nothing” or “silicon-on-insulator” wafers with tensile-strained silicon

A method of forming a substrate for use in CMOS fabrication comprising:

• preparing a silicon substrate, including doping a bulk silicon (100) substrate with ions taken from the group of ions to form a doped substrate taken from the group of doped substrates consisting of n-type doped substrates and p-type doped substrates;
• forming a first relaxed SiGe layer on the silicon substrate;
• forming a first tensile-strained silicon cap on the first relaxed SiGe layer;
• and
• completing a CMOS device on the tensile-strained silicon cap, wherein the CMOS device includes a source region and a drain region which are both in electrical contact with a tensile-strained silicon cap, including well ion implantation, threshold voltage adjustment, STI device isolation, gate oxidation, gate electrode and sidewall nitride formation;
• etching of gate oxide after formation of sidewall nitride;
• etching of exposed second tensile-strained silicon cap to expose second relaxed SiGe layer in the source region and the drain region;
• selectively laterally etching of any SiGe layer at the source and drain region and selectively laterally etching of any SiGe layer located beneath the gate and nitride spacers, forming a resulting tunnel, which is left empty or filled with a dielectric.

A method of forming a substrate for use in CMOS fabrication comprising:

• preparing a silicon substrate, including doping a bulk silicon (100) substrate with ions taken from the group of ions to form a doped substrate taken from the group of doped substrates consisting of n-type doped substrates and p-type doped substrates;
• forming a first relaxed SiGe layer on the silicon substrate, including forming a graded, relaxed SiGe layer to a thickness of between about 200 nm to 5 μm, and containing between about 10% and 100% Ge, and preferably between about 20% to 30% Ge;
• forming a first tensile-strained silicon cap on the first relaxed SiGe layer having a thickness of between about 10 nm to 50 nm;
• and
• completing a CMOS device on the tensile-strained silicon cap, wherein the CMOS device includes a source region and a drain region which are both in electrical contact with a tensile-strained silicon cap, including well ion implantation, threshold voltage adjustment, STI device isolation, gate oxidation, gate electrode and sidewall nitride formation;
• etching of gate oxide after formation of sidewall nitride;
• etching of exposed second tensile-strained silicon cap to expose second relaxed SiGe layer in the source region and the drain region;
• selectively laterally etching of any SiGe layer at the source and drain region and selectively laterally etching of any SiGe layer located beneath the gate and nitride spacers, forming a resulting tunnel, which is left empty or filled with a dielectric.