Transistor with vertical dielectric structure

A method for forming a transistor, the method comprising:

• patterning a layer of semiconductor material located over a dielectric to form a semiconductor structure;
• removing portions of the dielectric to form a dielectric structure, the semiconductor structure overlying the dielectric structure, wherein the dielectric structure has a height in a range of 80 to 200 nanometers;
• forming a layer of gate material including over the semiconductor structure and dielectric structure;
• forming a gate structure from the layer of gate material, wherein the gate structure comprises a first portion that is laterally adjacent to the semiconductor structure and a second portion that is laterally adjacent to the dielectric structure.

A method for forming a transistor, comprising:

• forming a dielectric structure of a vertical structure and forming a semiconductor structure of the vertical structure, the semiconductor structure overlying the dielectric structure, wherein the dielectric structure has a height in a range of 80 to 200 nanometers;
• forming a floating gate structure of the transistor adjacent to the vertical structure, the floating gate structure comprising a first portion that is laterally adjacent to the semiconductor structure and a second portion that is laterally adjacent to the dielectric structure;
• forming a control gate structure of the transistor, the control gate structure including a first portion that is laterally adjacent to the first portion of the floating gate structure, the control gate structure includes a second portion that is laterally adjacent to the second portion of the floating gate structure;
• wherein a channel region of the transistor is located in the semiconductor structure.