Method of manufacturing integrated semiconductor devices and related devices

A method of manufacturing integrated semiconductor devices, including the steps of:

• providing a layered semiconductor structure having an exposed surface, said layered structure including a base buffer layer opposite said exposed surface,
• providing a mask on said exposed surface thereby defining a masked region of said layered structure underneath said mask;
• said mask having a main direction of extension with a width across said main direction and an end portion,
• etching said layered structure over a given depth starting from said exposed surface into said base buffer layer, whereby said masked region is left substantially unaffected by said etching and has an end surface forming a vertical sidewall extending underneath said end portion of said mask to said base buffer layer,
• growing a further layered semiconductor structure around said masked region to produce an integrated layered semiconductor structure having at said end surface an interface between said layered structure and said further grown structure where layers of the further layered semiconductor structure are butt coupled to layers in the masked region, wherein said width is selected to be less than 50 microns.

A method of manufacturing integrated semiconductor devices, including the steps of:

• providing a layered semiconductor structure having an exposed surface,
• providing a mask on said exposed surface thereby defining a masked region of said layered structure underneath said mask;
• said mask having a main direction of extension with a width across said main direction and an end portion,
• etching said layered structure over a given depth starting from said exposed surface, whereby said masked region is left substantially unaffected by said etching and has an end surface forming a vertical sidewall extending underneath said end portion of said mask,
• growing a further layered semiconductor structure around said masked region to produce an integrated layered semiconductor structure having at said end surface an interface between said layered structure and said further grown structure where layers of the further layered semiconductor structure are butt coupled to layers in the masked region, wherein said width is selected to be less than 50 microns and wherein said etching is a combination of a reactive ion etching (RIE) and a wet chemical etch (WCE).

A method of manufacturing integrated semiconductor devices, including the steps of:

• providing a layered semiconductor structure having an exposed surface,
• providing a mask on said exposed surface thereby defining a masked region of said layered structure underneath said mask;
• said mask having a main direction of extension and an end portion,
• etching said layered structure over a given depth starting from said exposed surface, whereby said masked region is left substantially unaffected by said etching and has an end surface forming a vertical sidewall extending underneath said end portion, wherein said etch includes a chemical etch providing a nearly vertical sidewall beneath said end portion of said mask,
• growing a further layered semiconductor structure around said masked region to produce an integrated layered semiconductor structure having at said end surface an interface between said layered structure and said further grown structure where layers of the further layered semiconductor structure are butt coupled to layers in the masked region.