Method for fabricating a contact hole plane in a memory module

A method for fabricating a first contact hole plane in a memory module with an arrangement of memory cells each having a selection transistor, comprising:

• A) providing a semiconductor substrate with an arrangement of mutually adjacent gate electrode tracks on a surface of the semiconductor;
• B) producing an insulator layer on the semiconductor surface;
• C) forming a sacrificial layer on the insulator layer, where regions between the mutually adjacent gate electrode tracks are essentially filled and the gate electrode tracks are covered;
• D) forming material plugs on the sacrificial layer for defining contact openings between the mutually adjacent gate electrode tracks, wherein step D comprises the following steps D1′–D6′:
• D1′) depositing a hard mask layer on the sacrificial layer;
• D2′) depositing a resist layer on the hard mask layer;
• D3′) exposing the resist layer by a mask which defines the contact openings between the mutually adjacent gate electrode tracks;
• D4′) developing the resist layer to remove the exposed regions of the resist layer outside the contact openings between the mutually adjacent gate electrode tracks;
• D5′) anistropically etching the hard mask layer with the patterned resist layer as a mask;
• and
• D6′) removing the residual resist layer;
• E) anistropically etching the sacrificial layer, where the material plugs with the underlying sacrificial layer blocks;
• F) producing a vitreous layer with uncovering of the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks, where the regions between the mutually adjacent gate electrode tracks are essentially filled and an essentially planar surface is formed;
• G) etching sacrificial layer material from the vitreous layer for removing the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks;
• H) removing the uncovered insulator layer above the contact openings on the semiconductor surface between the mutually adjacent gate electrode tracks;
• and
• I) filling the contact opening regions with a conductive material, in the process forming an essentially planar surface with the surrounding vitreous layer.

A method for fabricating a first contact hole plane in a memory module with an arrangement of memory cells each having a selection transistor, comprising:

• A) providing a semiconductor substrate with an arrangement of mutually adjacent gate electrode tracks on a surface of the semiconductor;
• B) producing an insulator layer on the semiconductor surface;
• C) forming a sacrificial layer on the insulator layer, where regions between the mutually adjacent gate electrode tracks are essentially filled and the gate electrode tracks are covered;
• D) forming material plugs on the sacrificial layer for defining contact openings between the mutually adjacent gate electrode tracks, wherein step D comprises the following steps D1″–D9″:
• D1″) forming a hard mask layer on the sacrificial layer;
• D2″) planarizing the hard mask layer;
• D3″) depositing a resist layer on the hard mask layer;
• D4″) exposing the resist layer by a mask which defines the contact openings between the mutually adjacent gate electrode tracks;
• D5″) developing the resist layer in order to remove the exposed regions of the resist layer and to uncover the hard mask layer;
• D6″) anistropically etching of the hard mask layer with the patterned resist layer as a mask;
• D7″) removing the patterned resist layer;
• D8″) introducing a filling material into the etching openings in the hard mask layer;
• and
• D9″) removing the hard mask layer to form the material plugs made from the filling material on the sacrificial layer for defining contact openings between the mutually adjacent gate electrode tracks;
• E) anistropically etching the sacrificial layer, where the material plugs with the underlying sacrificial layer blocks;
• F) producing a vitreous layer with uncovering of the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks, where the regions between the mutually adjacent gate electrode tracks are essentially filled and an essentially planar surface is formed;
• G) etching sacrificial layer material from the vitreous layer for removing the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks;
• H) removing the uncovered insulator layer above the contact openings on the semiconductor surface between the mutually adjacent gate electrode tracks;
• and
• I) filling the contact opening regions with a conductive material, in the process forming an essentially planar surface with the surrounding vitreous layer.

A method for fabricating a first contact hole plane in a memory module with an arrangement of memory cells each having a selection transistor, comprising:

• A) providing a semiconductor substrate with an arrangement of mutually adjacent gate electrode tracks on a surface of the semiconductor;
• B) producing an insulator layer on the semiconductor surface;
• C) forming a sacrificial layer on the insulator layer, the regions between the mutually adjacent gate electrode tracks essentially being filled and the gate electrode tracks being covered;
• D) forming material plugs on the sacrificial layer for defining contact openings between the mutually adjacent gate electrode tracks;
• E) anistropically etching of the sacrificial layer, the material plugs with the underlying sacrificial layer blocks remaining;
• F) producing a vitreous layer with uncovering of the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks, the regions between the mutually adjacent gate electrode tracks essentially being filled and an essentially planar surface being formed;
• G) etching sacrificial layer material from the vitreous layer for removing the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks;
• H) removing the uncovered insulator layer above the contact openings on the semiconductor surface between the mutually adjacent gate electrode tracks;
• and
• I) filling the contact opening regions with a conductive material, in the process forming an essentially planar surface with the surrounding vitreous layer,
• wherein
• step C) comprises:
• C1′) depositing a first sacrificial layer on the insulator layer, the regions between the mutually adjacent gate electrode tracks essentially being filled and the gate electrode tracks being covered;
• C2′) planarizing the first sacrificial layer with uncovering of the gate electrode tracks, an essentially planar surface being formed;
• and
• C3′) depositing a second sacrificial layer.

A method for fabricating a first contact hole plane in a memory module with an arrangement of memory cells each having a selection transistor, comprising:

• A) providing a semiconductor substrate with an arrangement of mutually adjacent gate electrode tracks a surface of the semiconductor;
• B) producing an insulator layer on the semiconductor surface;
• C) forming a sacrificial layer on the insulator layer, the regions between the mutually adjacent gate electrode tracks essentially being filled and the gate electrode tracks being covered;
• D) forming material plugs on the sacrificial layer for defining contact openings between the mutually adjacent gate electrode tracks;
• E) anistropically etching of the sacrificial layer, the material plugs with the underlying sacrificial layer blocks remaining;
• F) producing a vitreous layer with uncovering of the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks, the regions between the mutually adjacent gate electrode tracks essentially being filled and an essentially planar surface being formed;
• G) etching sacrificial layer material from the vitreous layer for removing the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks;
• H) removing the uncovered insulator layer above the contact openings on the semiconductor surface between the mutually adjacent gate electrode tracks;
• and
• I) filling the contact opening regions with a conductive material, in the process forming an essentially planar surface with the surrounding vitreous layer,
• wherein
• step C) comprises:
• C1″) forming a plane first sacrificial layer on the insulator layer, the regions between the mutually adjacent gate electrode tracks essentially being filled and the gate electrode tracks being covered;
• and
• C2″) depositing a hard mask layer formed as a second sacrificial layer.