US 7,018,753 B2Granted

Variable mask field exposure

AssigneeLSI Logic Corporation

InventorsDavid J. Sturtevant, Duane B. Barber, Ann I. Kang

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Abstract

A method of fabricating integrated circuits according to a first design by imaging a first layer on a substrate using a first mask having a block of first patterns in common with a second design, but without any other patterns of the first or second designs and imaging a second layer on the substrate using a second mask having a block of second patterns unique to the first design and at least one third layer pattern. The block of first patterns is repeatedly exposed in a first grid and the block of second patterns is repeatedly exposed in a second grid, each without overlap in the corresponding layer. The grids are aligned such that the integrated circuits and test structures in scribe lines between the integrated circuits are properly formed on the substrate. The first patterns can be for large fields and the second patterns can be for small fields.

Claims3

Dependent claims

In a method of fabricating a plurality of integrated circuits on a substrate according to a first integrated circuit design, where each of the integrated circuits is formed with a plurality of layer patterns, where at least one first layer pattern of the layer patterns is common with a second integrated circuit design, and at least one second layer pattern of the layer patterns is unique to the first integrated circuit design, the improvement comprising the steps of:

imaging the at least one first layer pattern on the substrate using a first mask having a first number of first layer patterns according to the first integrated circuit design formed in a block thereon, with no other layer patterns formed on the first mask, where the first layer patterns are imaged on the substrate by exposing and repeating the block of first layer patterns across the substrate according to a first grid without overlapping the block of first layer patterns, and
imaging the at least one second layer pattern on the substrate using a second mask having a second number of second layer patterns according to the first integrated circuit design formed in a block thereon, where the second number is less than the first number with at least one additional layer pattern formed on the second mask, where the second layer patterns are imaged on the substrate by exposing and repeating the block of second layer patterns across the substrate according to a second grid without overlapping the block of second layer patterns,
where the first grid and the second grid are aligned such that each integrated circuit and test structures in scribe lines between the integrated circuits are properly formed on the substrate according to the first integrated circuit design.

Dependencies are inferred from the claim text.

Facts

Application: 10/429,376Filed 5 May 2003
Published: US 2004/0224236 A111 Nov 2004
Granted: 28 Mar 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G03F 7/70433
Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating…
G03F 1/00
Originals for photomechanical production of textured or patterned surfaces
G03F 1/50
Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles…
G03F 7/70466
Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating…