Method of verifying the placement of sub-resolution assist features in a photomask layout
AssigneeInternational Business Machines Corporation
InventorsYuping Cui, Rama Nand Singh
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AssigneeInternational Business Machines Corporation
InventorsYuping Cui, Rama Nand Singh
Estimating the term…
A method of verifying the placement of sub-resolution assist features (SRAFs) in a photomask layout is described. SRAFs are added to the photomask layout to enhance the process window for semi-isolated and isolated features. Rules are provided to automatically place the SRAFs into the layout. When deficiencies are detected in the assist feature design or in the automated SRAF placement program, the placement of SRAFs requires verification. The method verifies the correct placement by defining a unique image property linked to the accurate placement of the assist features, and combines it with in-situ image simulation of the individual layout. The placement of the SRAFs is verified by: 1) formulating a unique image property using a technology specific representative sample design with and without properly placed SRAFs; 2) simulating the resist image of each individual device layout in the photomask, considering the layout environment of each individual device, and analyzing the unique image properties associated with the device being examined; 3) sorting the geometric properties of each device into predetermined category; and 4) for each individual device layout, examining the image property value and geometric category values, and determining whether the device is adequately surrounded by SRAFs. If not, individual device on the photomask layout are marked with error marker shapes to be subsequently corrected.
A method of verifying the presence and the placement of sub-resolution assist features (SRAFs) in a photomask layout of an integrated circuit (IC) chip design, comprising the steps of:
A method for verifying the presence and the placement of sub-resolution assist features (SRAFs) in a photomask layout on an integrated circuit (IC) chip design comprising the steps of:
A method for verifying the presence and the placement of sub-resolution assist features (SRAFs) in a photomask layout of an integrated circuit (IC) chip design representing an electric circuit comprising the steps of:
An article of manufacture comprising a computer-usable medium having computer readable program code means embodied therein for verifying the placement of sub-resolution assist features (SRAFs) in a photomask layout of an integrated circuit (IC) chip design, the computer readable program code means in said article of manufacture comprising:
A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method of verifying the placement of sub-resolution assist features (SRAFs) in a photomask layout of an integrated circuit (IC) chip design, said method steps comprising:
Dependencies are inferred from the claim text.