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US 7,016,226 B2Granted
Semiconductor memory device for storing multivalued data
AssigneeKabushiki Kaisha Toshiba
InventorsNoboru Shibata, Tomoharu Tanaka
Life of this patent
Estimating the term…
Abstract
Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction.
Claims7
A semiconductor memory device comprising:
- a memory cell array configured by arranging a plurality of memory cells in a matrix, each of, which is capable of having one of four threshold voltages and storing two bits of data;
- a plurality of bit lines, each of which is connected to said plurality of memory cells arranged in the column direction;
- a plurality of word lines, each of which is connected to said plurality of memory cells arranged in the row direction;
- a first flag cell and a second flag cell which are selected at the same time when the memory cells are selected by each of the word lines;
- and
- a control section which, when writing the data in a second page composed of the two bits into the memory cells selected by the word line, writes specific data into the first and second flag cells and which, when reading the data in a first page from the memory cells, determines from the data read from the first flag cell whether the second page has been written into the memory cells and which, when reading the data in the second page from the memory cells, determines from the data read from the second flag cell whether the second page has been written into the memory cells.
3 more elements
Dependencies are inferred from the claim text.