US 7,016,214 B2Granted

Semiconductor integrated circuit device

AssigneeHitachi, Ltd.

InventorsTsuneo Kawamata, Masatoshi Hasegawa, Keinosuke Toriyama, Tomofumi Hokari

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Abstract

A semiconductor integrated circuit device capable of achieving higher integration and simplification of manufacturing processes is provided. Circuitry is provided which includes a first N-channel MOSFET and a first p-channel MOSFET each having a gate insulating dielectric film with a first film thickness, wherein a poly-silicon layer making up a gate electrode is doped with an N-type impurity. The circuitry also includes a second N-channel MOSFET having a gate insulator film with a second film thickness thinner than the first thickness, wherein an N-type impurity is doped into a polysilicon layer making up a gate electrode, and a second P-channel MOSFET with a P-type impurity being doped into a polysilicon layer making up a gate electrode. The gate electrodes of the first N-channel MOSFET and first P-channel MOSFET are integrally formed and mutually connected together.

Claims10

Dependent claims

A semiconductor integrated circuit device comprising a plurality of first circuits each being such that a gate of a MOSFET of first conductivity type and a gate of a MOSFET of second conductivity type are commonly connected together for use as a first input terminal, a source of the first conductivity type MOSFET is for use as a second input terminal, a ground potential of circuitry is given to a source of the second conductivity type MOSFET, and a drain of the first conductivity type MOSFET and a drain of the second conductivity type MOSFET are common-connected together for use as an output terminal, wherein

said first conductivity type MOSFET is such that one gate electrode has a rectangular shape whereas said second conductivity type MOSFET is such that two adjacent gate electrodes exhibit a rectangular shape while letting these rectangular gate electrodes be laid out so that pitches thereof are equal to each other, and
first input terminals of the plurality of first circuits are mutually connected by a wiring layer forming the gate electrodes.

Dependencies are inferred from the claim text.

Facts

Application: 10/957,712Filed 5 Oct 2004
Priority: JP 2003-3465006 Oct 2003
Published: US 2005/0077582 A114 Apr 2005
Granted: 21 Mar 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G11C 11/4087
Address circuits: address decoders, e.g. bit - or word line decoders; Multiple line decoders
G11C 11/4097
Read-write [R-W] circuits: bit-line organisation, e.g. bit-line layout, folded bit lines
H10D 84/8314
Of only insulated-gate FETs [IGFET]: the IGFETs characterised by having gate insulating layers with different properties
H10D 84/856
Complementary IGFETs, e.g. CMOS: the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS