Power-on reset circuit with low standby current and self-adaptive reset pulse width

A power-on reset circuit for an integrated circuit, the power-on reset circuit comprising:

• a self-regulating current source providing a regulated current and a plurality of output currents derived from and proportional to the regulated current;
• a voltage threshold detector circuit coupled to monitor a power supply voltage of the integrated circuit and generating a first signal, the voltage threshold detector circuit being biased by at least a first output current of the self-regulating current source and operating to detect power supply voltage events including AC voltage edges and DC voltage edges, wherein the voltage threshold detector circuit asserts the first signal when a power supply voltage event is detected and deasserts the first signal when the power supply voltage event has expired;
• a DC biasing start-up circuit receiving the first signal from the voltage threshold detector circuit and a second output current of the self-regulating current source, the DC biasing start-up circuit providing a start-up current to the integrated circuit and providing a first control signal wherein the start-up current is generated and the first control signal is deasserted in response to the deassertion of the first signal;
• a counter circuit receiving the first control signal and providing a second control signal, the counter circuit being enabled to count a predetermined number of cycles when the first control signal is deasserted and the counter circuit deasserting the second control signal when the predetermined number of cycles has been counted;
• a gated ring oscillator receiving the second control signal and providing an oscillator output signal to the counter circuit as a clock signal, the gated ring oscillator being disabled when the second control signal is deasserted;
• and
• a first logic gate performing a logical OR operation of the first signal and the second control signal and generating a reset signal for the integrated circuit,
• wherein the reset signal is asserted when the first signal is asserted and the reset signal is deasserted when both the first signal and the second control signal are deasserted, thereby generating a reset pulse for the integrated circuit.