Tileable field-programmable gate array architecture

An apparatus comprising a routing structure for a field programmable gate array (FPGA), the FPGA comprising:

• a first FPGA tile comprising:
• a plurality of logic components, at least one of said logic components having a first, second and third set of input ports and having a first and second set of output ports;
• a first set of routing conductors disposed within said first FPGA tile programmably coupled to said first set of output ports of said logic components and configured to receive signals, route signals within said first FPGA tile, and provide said signals to said first set of input ports of said logic components, said first set of routing conductors comprising a plurality of horizontal routing buses and a plurality of vertical routing buses, wherein at least one of said plurality of horizontal routing buses forms an intersection with at least one of said plurality of vertical routing buses at a routing interconnect area;
• a second set of routing conductors disposed across said first FPGA tile and at least one other FPGA tile, independent of said first set of routing conductors coupled to said second set of output ports and that is configured to receive, select and route signals around said first FPGA tile and within said first FPGA tile, and provide said signals to said second set of input ports of said logic components;
• and
• a third set of routing conductors disposed across said first FPGA tile, independent of said first and second set of routing conductors, coupled to at least one of said first output ports of said logic components and configured to receive signals, route signals around said first FPGA tile and within said first FPGA tile, and provide said signals to said third set of input ports of said logic components.