Method of designing custom circuit device using scheduling clock cycles

A method of designing a custom circuit device, which begins with a high level architecture of subsystems coupled by virtual wires, comprising the steps of:

• spatially placing the subsystems onto tiles, thereby forming subsystem placements, each of the tiles comprising a circuit;
• routing the virtual wires that cross boundaries of the tiles onto an interconnect architecture, the interconnect architecture comprising switches and registers such that some of the switches route a signal from a first subsystem located on a first tile to a second subsystem located on a second tile and further such that at least two of the registers consecutively latch the signal at a time interval of no more than a repeating time period;
• scheduling of tasks according to clock cycles;
• and
• mapping the subsystems and the virtual wires that do not cross the boundaries of the tiles onto the circuits of the tiles according to the subsystem placements.

A method of designing a custom circuit device, which begins with a high level architecture of subsystems coupled by virtual wires, comprising the steps of:

• spatially placing the subsystems onto tiles;
• routing the virtual wires that cross boundaries of the tiles onto an interconnect architecture, the interconnect architecture comprising switches and registers such that some of the switches route a signal from a first subsystem located on a first tile to a second subsystem located on a second tile and further such that at least two of the registers consecutively latch the signal at a time interval of no more than a clock cycle period;
• and
• scheduling of tasks according to clock cycles.

A computer readable memory comprising computer code for implementing a method of designing a custom circuit device, which begins with a high level architecture of subsystems coupled by virtual wires, the method of designing the custom circuit device comprising the steps of:

• spatially placing the subsystems onto tiles;
• routing the virtual wires that cross boundaries of the tiles onto an interconnect architecture, the interconnect architecture comprising switches and registers such that some of the switches route a signal from a first subsystem located on a first tile to a second subsystem located on a second tile and further such that at least two of the registers consecutively latch the signal at a time interval of no more than a repeating time period;
• and
• scheduling of tasks according to clock cycles.

A computer readable memory comprising computer code for implementing a method of designing a custom circuit device, which begins with a high level architecture of subsystems coupled by virtual wires, the method of designing the custom circuit device comprising the steps of:

• spatially placing the subsystems onto tiles, thereby forming subsystem placements, each of the tiles comprising a circuit;
• routing the virtual wires that cross boundaries of the tiles onto an interconnect architecture, the interconnect architecture comprising switches and registers such that some of the switches route a signal from a first subsystem located on a first tile to a second subsystem located on a second tile and further such that at least two of the registers consecutively latch the signal at a time interval of no more than a repeating time period;
• scheduling of tasks according to clock cycles;
• and
• mapping the subsystems and the virtual wires that do not cross the boundaries of the tiles onto the circuits of the tiles according to the subsystem placements.

A computer readable memory comprising computer code for implementing a method of designing a custom circuit device, which begins with a high level architecture of subsystems coupled by virtual wires, the method of designing the custom circuit device comprising the steps of:

• spatially placing the subsystems onto tiles;
• routing the virtual wires that cross boundaries of the tiles onto an interconnect architecture, the interconnect architecture comprising switches and registers such that some of the switches route a signal from a first subsystem located on a first tile to a second subsystem located on a second tile and further such that at least two of the registers consecutively latch the signal at a time interval of no more than a clock cycle period;
• and
• scheduling of tasks according to clock cycles.