Method for converting a planar transistor design to a vertical double gate transistor design

A method for converting a planar transistor design to a vertical double-gate transistor design, comprising:

• providing a planar transistor layout corresponding to the planar transistor design having a gate layer overlying an active layer;
• performing an AND function between the gate layer and active layer to define a first intermediate layer;
• defining a second intermediate layer based on the first intermediate layer, the second intermediate layer defining a spacing between at least two fins of the vertical double-gate transistor design;
• and
• performing an XOR function between the second intermediate layer and the active layer to define a resulting layer, the resulting layer for use in creating at least a portion of a mask corresponding to the vertical double-gate transistor design.

A method for converting a planar transistor design to a vertical double-gate transistor design stored via a computer readable medium, said computer readable medium comprising:

• a first set of instructions for receiving a planar transistor layout corresponding to the planar transistor design having a gate layer overlying an active layer;
• a second set of instructions for defining a first intermediate layer based on an overlapping region of the gate layer and the active layer;
• a third set of instructions for using the first intermediate layer to define a second intermediate layer, the second intermediate layer for defining a spacing between at least two fins of the vertical double-gate transistor design;
• and
• a fourth set of instructions for defining a resulting layer based on a non-overlapping region of the at least one intermediate layer and the active layer, the resulting layer for use in creating at least a portion of a mask corresponding to the vertical double-gate transistor design.