Method, program, and apparatus for designing a semiconductor device
AssigneeFujitsu Limited
InventorsHisayoshi Ohba, Jun Watanabe
Life of this patent
Estimating the term…
Abstract
A method for designing a semiconductor device in which dummy pattern density and design pattern density are equalized on the entire semiconductor chip. A layout pattern for a layout layer in a semiconductor device is divided into divided areas (step S1). A dummy pattern is inserted between design patterns in the divided areas obtained by dividing the layout pattern (step S2). Dummy pattern density and design pattern density in each divided area are calculated (step S3). Pattern rules for a dummy pattern in each divided area are changed so that the dummy pattern density and the design pattern density will be desired values (step S4).
Claims12
A method for designing a semiconductor having a computer for inserting a dummy pattern between design patterns, the method comprising the steps of:
- dividing a layout pattern for a layout layer in a semiconductor device into divided areas;
- inserting a dummy pattern between design patterns in the divided areas;
- calculating the density of the dummy pattern and the design patterns in each of the divided areas;
- and
- changing pattern rules for the dummy pattern so that the density will be desired values.
A program for designing a semiconductor device which inserts a dummy pattern between design patterns, the program making a computer perform the processes of:
- dividing a layout pattern for a layout layer in a semiconductor device into divided areas;
- inserting a dummy pattern between design patterns in the divided areas;
- calculating the density of the dummy pattern and the design patterns in each of the divided areas;
- and
- changing pattern rules for the dummy pattern so that the density will be desired values.
A computer-readable record medium which stores a program for designing a semiconductor device which inserts a dummy pattern between design patterns, the program making a computer perform the processes of:
- dividing a layout pattern for a layout layer in a semiconductor device into divided areas;
- inserting a dummy pattern between design patterns in the divided areas;
- calculating the density of the dummy pattern and the design patterns in each of the divided areas;
- and
- changing pattern rules for the dummy pattern so that the density will be desired values.
An apparatus for designing a semiconductor device which inserts a dummy pattern between design patterns, the apparatus comprising:
- a dividing section for dividing a layout pattern for a layout layer in a semiconductor device into divided areas;
- an inserting section for inserting a dummy pattern between design patterns in the divided areas;
- a calculating section for calculating the density of the dummy pattern and the design patterns in each of the divided areas;
- and
- a changing section for changing pattern rules for the dummy pattern so that the density will be desired values.
Dependencies are inferred from the claim text.