Delay diagnosis method for semiconductor integrated circuit, computer program product for diagnosing delay of semiconductor integrated circuit and computer readable recording medium recording program thereon

A program product causing a computer to execute a delay diagnosis method for a semiconductor integrated circuit including a plurality of blocks, said program product having program steps of:

• inputting register transfer level logic information including connection information of said blocks, and floor plan information including positional information of each block on said semiconductor integrated circuit;
• finding a register as the end point of a path or a register as the start point of said path connected to edges or the number of edges from said logic information;
• computing the logic stage number of said path from said a start point register of said path or said edge number;
• finding block-to-block distances from said floor plan information when said path extends over a plurality of blocks;
• computing intra-block delays from said logic stage number and gate unit-value delays;
• computing inter-block delays from said block-to-block distances and routing unit-value delays;
• and
• diagnosing if the delay of said path can be converged within a target path delay from the relation among said computed intra-block delays, said computed inter-block delays and said target path delay.

A recording medium having a program recorded therein so that a computer can read said program and execute, according to said program, a delay diagnosis method of diagnosing delay in a semiconductor integrated circuit having a plurality of blocks, said program comprising the steps of:

• inputting register transfer level logic information including connection information of said blocks, and floor plan information including positional information of each block on said semiconductor integrated circuit;
• finding a register as the end point of a path or a register as the start point of said path connected to edges or the number of edges from said logic information;
• computing the logic stage number of said path from a start point register of said path or said edge number;
• finding block-to-block distances from said floor plan information when said path extends over a plurality of blocks;
• computing intra-block delays from said logic stage number and gate unit-value delays;
• computing inter-block delays from said block-to-block distances and routing unit-value delays;
• and
• diagnosing if the delay of said path can be converged within a target path delay from the relation among said computed intra-block delays, said computed inter-block delays and said target path delay.