Method for modeling integrated circuit yield

A method for predicting manufacturing yield for an integrated circuit, comprising in the order recited:

• (a) assigning different integrated circuit library elements into circuit types according to a user defined list of attributes;
• (b) compiling a set of yield limiting parameters for each circuit type and determining a normalization factor for each circuit type;
• (c) selecting library elements from said design database to include in a proposed design for said integrated circuit;
• (d) generating an equivalent circuit count of said proposed design based on said normalization factors for said circuit types and a count of each different library element included in said proposed design;
• and
• (e) calculating a predicted manufacturing yield based on said equivalent circuit count, a defect density value and an area of said proposed integrated circuit chip.

A computer system comprising a processor, an address/data bus coupled to said processor, and a computer-readable memory unit adapted to be coupled to said processor, said memory unit containing instructions that when executed by said processor implement a method for predicting manufacturing yield for an integrated circuit, said method comprising the computer implemented steps of:

• (a) providing a multiplicity of different integrated circuit library elements in a design database, each library element linked to a corresponding normalization factor in said design database;
• (b) selecting library elements from said design database to include in a proposed design for said integrated circuit;
• (c) generating an equivalent circuit count of said proposed design based on said normalization factors and a count of each different library element included in said proposed design;
• and
• (d) calculating a predicted manufacturing yield based on said equivalent circuit count, a predicted density of manufacturing defects and an area of said proposed integrated circuit chip.