Dynamically reconfigurable precision signal delay test system for automatic test equipment

A circuit for generating signals for an Automatic Testing Equipment (ATE) system, said circuit comprising:

• a pattern memory for containing pattern data for application to a set of tester pins;
• a single programmable time event generator receiving a master clock and containing a set of programmable values for specifying relative time positions of timing signals with respect to said master clock;
• and
• a plurality of coarse timing circuits coupled to said master clock, said single programmable time event generator and said pattern memory, wherein said coarse timing circuits are for applying said pattern data to said set of tester pins with said relative time positions of said master clock.

A circuit for capturing signals from a device under test in an Automatic Testing Equipment (ATE) system, said circuit comprising:

• a pattern memory for containing pattern data for application to a first set of tester pins;
• a single programmable time event generator receiving a master clock and containing a set of programmable values for specifying relative time positions of timing signals with respect to said master clock and coupled to said pattern memory;
• and
• a plurality of coarse timing circuits coupled to said master clock, said single programmable time event generator, wherein said coarse timing circuits are for capturing output data from a second set of tester pins using said relative time positions of said master clock.