Test method and test system for semiconductor device
AssigneeFujitsu Limited
InventorsMasayuki Takeshige, Sumitaka Hibino, Kenji Yamada
Life of this patent
Estimating the term…
Abstract
Method and system for shortening the time needed to test a semiconductor device having a plurality of memory circuits. The semiconductor device includes an address decoder for selecting a plurality of memory circuits and causing the memory circuits to perform a read/write operation. A comparator receives plural pieces of read data read from the plurality of memory circuits and compares the plural pieces of read data with one another. A processing unit compares one of the plural pieces of read data with write data. Using the comparison results of the comparator and the processing unit shorten the time needed to test the plurality of memory circuits.
Claims18
A method of testing a plurality of memory circuits included in a semiconductor device, comprising steps of:
- selecting the plurality of memory circuits and causing the memory circuits to perform a read/write operation;
- comparing plural pieces of read data read from the plurality of memory circuits in a read operation with one another and generating a first signal as first comparison results;
- comparing one of the plural pieces of read data, which is read from a predetermined one memory circuit, with write data and generating a second signal as a second comparison result in parallel with the first signal;
- and
- testing the plurality of memory circuits based on the first and second signals.
A semiconductor device comprising:
- a plurality of memory circuits each of which performs data writing and data reading;
- a processing unit coupled to the plurality of memory circuits for accessing one of the plurality of memory circuits for data writing and data reading by supplying an address signal thereto;
- an address decoder coupled to the processing unit for receiving the address signal and generating a plurality of select signals for selecting the plurality of memory circuits in a test mode, wherein the plurality of memory circuits perform data writing and data reading in accordance with the plurality of select signals;
- a multiplexer coupled to the plurality of memory circuits and the processing unit for supplying the processing unit with read data read from a predetermined one memory circuit which is accessed by the processing unit;
- and
- a comparator coupled to the plurality of memory circuits for comparing plural pieces of read data respectively read from the plurality of memory circuits with one another in the test mode and generating a first signal as first comparison results, wherein in the test mode, the processing unit compares data written in the plurality of memory circuits with one of the plural pieces of read data read from the predetermined one memory circuit and supplied from the multiplexer and generates a second signal as a second comparison result to test the plurality of memory circuits based on the first and second signals, wherein the comparator generates the second signal in parallel with the first signal.
A system for testing a plurality of memory circuits included in a semiconductor device, comprising:
- an address decoder for selecting the plurality of memory circuits and causing the memory circuits to perform a read/write operation;
- a comparator for receiving plural pieces of read data read from the plurality of memory circuits and comparing the plural pieces of read data with one another to generate a first signal as first comparison results;
- and
- a processing unit for comparing one of the plural pieces of read data, which is read from a predetermined memory circuit, with write data and generating a second signal as a second comparison result to test the plurality of memory circuits based on the first and second signals, wherein the processing unit generates the second signal in parallel with the first signal.
Dependencies are inferred from the claim text.