Method, apparatus, and system for high speed data transfer between electronic devices

An apparatus comprising:

• a first device to transmit a plurality of data signals in a parallel format;
• and
• a second device to receive the plurality of data signals from the first device,
• wherein the second device detects phase information of each data signal with respect to a corresponding clock signal and adjusts a delay of the respective data signal based on the phase information detected prior to sampling of the data signals and the second device transmits parallel data sample to the first device, subsequent to the sampling of the data signals.

A method comprising:

• transmitting a plurality of data signals in parallel mode from a first device to a second device over a first bus;
• detecting phase information of each data signal received at the second device against a corresponding clock signal;
• sending the phase information from the second device to the first device, wherein the phase information is sent from the second device to the first device in a serial mode;
• and
• adjusting an output delay of each data signal at the first device based on the phase information received from the second device.

A method comprising:

• transmitting a plurality of data signals from a first device to a second device in a parallel mode over a first bus;
• detecting, at the second device, phase information of each data signal with respect to a corresponding clock signal;
• adjusting a delay of the respective data signal prior to sampling of the data signal at the second device;
• sending a parallel data sample from the second device to the first device;
• and
• upon receiving the parallel data sample at the first device, comparing the parallel data sample with a programmed parallel data pattern.

A system comprising:

• a processor;
• a first component coupled to the processor;
• and
• a second component coupled to the first component, wherein the first component transmits data words to the second component in parallel mode, each data word including a plurality of data bits, wherein the second component detects phase information of each data bit relative to a corresponding clock signal and feeds back the phase information of each data bit to the first component, the first component adjusts an output delay of each data bit based on the phase information fed back from the second component, wherein the second component samples parallel data patterns received from the first component and feeds back the sampled data patterns to the first component.

A machine-readable medium comprising instructions which, when executed by a machine, cause the machine to perform operations including:

• transmitting a plurality of data signals in parallel mode from a first device to a second device over a first bus;
• detecting phase information of each data signal received at the second device against a corresponding clock signal;
• sending the phase information from the second device to the first device;
• adjusting an output delay of each data signal at the first device based on the phase information received from the second device;
• sampling and holding, at the second device, a parallel data pattern received from the first device;
• feeding back the sampled data from the second device to the first device;
• recognizing, at the first device, phase variations that are in excess of one bit of the sampled data fed back from the second device;
• and
• shifting data bit positions between parallel words to align phase variations that are in excess of one bit interval.

An apparatus comprising:

• a first device to transmit a plurality of data signals in a parallel mode;
• and
• a second device coupled to receive the plurality of data signals from the first device;
• wherein the second device detects phase information of each data signal against a corresponding clock signal and feeds back the phase information to the first device, the first device adjusts an output delay of each data signal based on the phase information fed back from the second device and the second device samples parallel data patterns transmitted from the first device and feeds back the sampled data to the first device.

An apparatus comprising:

• a first device to transmit a plurality of data signals in parallel mode;
• and
• a second device coupled to receive the plurality of data signals from the first device,
• wherein the second device detects phase information of each data signal against a corresponding clock signal and feeds back the phase information to the first device, the first device adjusts an output delay of each data signal based on the phase information fed back from the second device;
• and
• wherein the first device detects phase variations that are in excess of one bit of the sampled data fed back from the second device and shifts data bit positions between parallel data words to align phase variations that are in excess of one bit interval.

A method comprising:

• transmitting a plurality of data signals in parallel mode from a first device to a second device over a first bus;
• detecting phase information of each data signal received at the second device against a corresponding clock signal;
• sending the phase information from the second device to the first device;
• adjusting an output delay of each data signal at the first device based on the phase information received from the second device;
• sampling and holding, at the second device, parallel data pattern received from the first device;
• feeding back the sampled data from the second device to the first device;
• recognizing, at the first device, phase variations that are in excess of one bit of the sampled data fed back from the second device;
• and
• shifting data bit positions between parallel words to align phase variations that are in excess of one bit interval.

A system comprising:

• a processor;
• a first component coupled to the processor;
• and
• a second component coupled to the first component, wherein the first component transmits data words to the second component in parallel mode, each data word including a plurality of data bits, wherein the second component detects phase information of each data bit relative to a corresponding clock signal and feeds back the phase information of each data bit to the first component, the first component adjusts an output delay of each data bit based on the phase information fed back from the second component;
• wherein the first component receives data words from the second component in a parallel mode, each data words including a plurality of data bits, and wherein the first component detects phase information of each data bit relative to a corresponding clock signal and adjusts a delay of the respective data bit based on the phase information detected prior to sampling of the data bits.