Semiconductor integrated circuit characterized by timing adjustment of clock switching control

A semiconductor integrated circuit comprising:

• a clock control circuit having a reference clock input thereto, which generates a control basic clock to be used to implement clock control on a central processing unit;
• and
• a microcontroller that includes said central processing unit and a clock generation control circuit that controls the generation of said control basic clock at said clock control circuit in conformance to an instruction issued by said central processing unit, wherein:
• said clock control circuit includes:
• a status shift circuit that generates a frequency divided clock by shifting the status of a signal level in correspondence to a value indicated by a clock frequency division setting signal transmitted from said clock generation control circuit;
• a switching timing generation circuit that measures the timing with which a switch between said reference clock and said frequency divided clock is made;
• and
• a selection switching circuit that generates said control basic clock by switching between said reference clock and said frequency divided clock,
• wherein said status shift circuit individually generates frequency divided clocks with varying cycles.