Synthesizing a pixel clock with extremely close channel spacing
AssigneeSun Microsystems, Inc.
InventorNathaniel David Naegle
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Abstract
A graphic system may include a pixel synthesizing device that uses two or more phase-locked loops (PLL's) in tandem in order to achieve a better M/N ratio. The two PLL's connected in tandem have an effective M/N ratio of (M1*M2)/(N1*N2). The pixel synthesizing device is operable to synthesize free-running (non-genlocked, or sync-master) pixel clock frequencies using a much greater variety of M and N. As a result, greater precision in specification of the pixel clock frequency is achieved, yielding greater precision in a frame rate of a particular video format. As a result, the allowable channel spacing is greatly increased, and the graphic system can select from a wide range of ultradense spaced pixel clocks.
Claims20
A device for synthesizing a pixel clock signal with improved precision in specification of the signal frequency, the device comprising:
- a local timebase signal of a first frequency;
- a first phase-locked loop circuit operable to receive the local timebase signal and operate on the local timebase signal to produce an intermediate signal of an intermediate frequency;
- and
- a second phase-locked loop circuit operable to receive the intermediate signal and operate on the intermediate signal to produce a final signal of a final frequency;
- wherein internal multiplier and divisor factors for the second phase-locked loop circuit are selected so that the ratio of the multiplier factor divided by the divisor factor is near unity.
A method to synthesize an ultradense pixel clock signal, the method comprising:
- generating a local timebase signal of a first frequency;
- a first phase-locked loop circuit receiving the local timebase signal and operating on the local timebase signal to produce an intermediate signal of an intermediate frequency;
- and
- a second phase-locked loop circuit receiving the intermediate signal and operating on the intermediate signal to produce a final signal of a final frequency;
- wherein internal multiplier and divisor factors for each phase-locked loop circuit are selected so that the final frequency divided by the intermediate frequency is near unity, and
- wherein the final signal is operable to serve as a pixel clock signal.
A graphics system, comprising:
- one or more filtering units, wherein the one or more filtering units are operable to filter samples and thereby produce pixels, wherein each one of the one or more filtering units comprises one or more pixel synthesizing devices, wherein the one or more pixel synthesizing devices are operable to produce an ultradense pixel clock signal for the graphic system;
- wherein each one of the one or more pixel synthesizing devices comprises:
- a local timebase signal of a first frequency;
- a first phase-locked loop circuit operable to receive the local timebase signal and operate on the local timebase signal to produce an intermediate signal of an intermediate frequency;
- a second phase-locked loop circuit operable to receive the intermediate signal and operate on the intermediate signal to produce a final signal of a final frequency, wherein the second phase-locked loop circuit has a loop bandwidth wider than a loop bandwidth of the first phase-locked loop circuit.
Dependencies are inferred from the claim text.