Processor capable of preventing sleep/hold state based on a difference between a processing block address and a writing block address
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsShiro Shimizu, Tsuyoshi Takayama, Hiroshi Yasuda
Life of this patent
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Abstract
The present invention provides a clock control type processor which can permit and accommodate a temporary delay in a processing operation also in a system in which processing times are not constant, and realize the accommodation while reducing the power consumption as much as possible. In this clock control type processor, a block difference detection circuit 20 detects a difference between a processing block address and a writing block address and outputs a block difference signal 105, and a clock control circuit 16 controls a clock.
Claims26
A processor including:
- storage means for storing inputted data;
- writing means for writing the inputted data in the storage means;
- processing means for reading data from the storage means and for processing the data;
- reading means for reading, from the storage means, data processed by the processing means;
- address generation means for generating an address in the storage means for the writing means, the processing means, or the reading means to perform writing/reading into/from the storage means;
- clock control means for switching between a normal state in which a clock signal is supplied to the processing means, and a sleep state in which the supply of the clock signal is stopped;
- and
- clock signal state switch means for preventing the clock control means from switching to the sleep state if the address generation means is in a predetermined state when the processing means finishes processing.
A processor including:
- storage means for storing inputted data;
- writing means for writing the inputted data in the storage means;
- processing means for reading data from the storage means and for processing the data;
- reading means for reading, from the storage means, data processed by the processing means;
- address generation means for generating an address in the storage means for the writing means, the processing means, or the reading means to perform writing/reading into/from the storage means;
- flipflop control means for controlling a flipflop included in the processing means to switch between a hold state in which data are held in a loop including the flipflop, and a normal state in which data are inputted/outputted into/from the flipflop;
- and
- hold means for preventing the flipflop control means from switching to the hold state if the address generation means is in a predetermined state when the processing means finishes processing.
Dependencies are inferred from the claim text.