Method for managing power in a simultaneous multithread processor by loading instructions into pipeline circuit during select times based on clock signal frequency and selected power mode

A simultaneous multithread (SMT) processor comprising:

• a pipeline circuit for processing instructions from first and second threads;
• circuitry for determining an instruction execution priority for each of said first and second threads and setting a selected power mode;
• circuitry for selecting said first thread for a first select time and said second thread for a second select time in response to said a selected power mode and a clock signal;
• and
• circuitry for loading instructions into said pipeline circuit during said first and second select times in response to a frequency of said clock signal.

A data processing system comprising:

• a central processing unit (CPU) having one or more simultaneous multithread (SMT) processors;
• a random access memory (RAM);
• an input output (I/O) adapter;
• a communications adapter;
• a bus coupling said CPU, RAM, I/O adapter, and said communications adapter;
• a pipeline circuit in said SMT processor for processing instructions from first and second threads;
• circuitry for determining an instruction execution priority for each of said first and second threads and setting a selected power mode;
• circuitry for selecting said first thread for a first select time and said second thread for a second select time in response to said a selected power mode and a clock signal;
• and
• circuitry for loading instructions into said pipeline circuit during said first and second select times in response to a frequency of said clock signal.