Apparatus and method for managing a processor pipeline in response to exceptions

A pipelined processor comprising:

• interrupt logic configured to indicate that an interrupt is pending;
• determining logic configured to determine whether execution of a current instruction within an execute stage of the pipelined processor will impact the execution of the pending interrupt;
• and
• flush logic configured to flush only instructions between the current instruction and a first instruction associated with the pending interrupt.

A processor comprising:

• a plurality of logic components organized in a pipeline, wherein one of the logic components is an execute component;
• a mechanism for indicating that an exception is pending;
• logic capable of determining whether execution of a current instruction within the execute component will impact the execution of the pending exception;
• and
• logic capable of performing a partial flush of the pipeline, wherein only instructions between the current instruction and a first instruction associated with the pending exception are flushed.